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    Thin gate stack structure for non-volatile memory cells and methods for forming the same
    1.
    发明申请
    Thin gate stack structure for non-volatile memory cells and methods for forming the same 审中-公开
    用于非易失性存储单元的薄栅堆叠结构及其形成方法

    公开(公告)号：US20090067256A1

    公开(公告)日：2009-03-12

    申请号：US11899644

    申请日：2007-09-06

    申请人： Arup Bhattacharyya ,  Garo Derderian

    发明人： Arup Bhattacharyya ,  Garo Derderian

    IPC分类号： G11C11/34 ,  H01L21/336 ,  H01L29/788

    CPC分类号： H01L29/42324 ,  G11C2207/2245 ,  H01L29/40114 ,  H01L29/40117

    摘要： Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over the tunnel dielectric material to store electrical charge. The storage medium is disposed between a first interface material and a second interface material, each interface material provides a smoother interface between the storage medium and surrounding dielectric materials. A charge blocking material is formed over the storage medium, followed by a control gate material.

    摘要翻译： 描述了用于降低存储器件中的存储器单元的编程电压的实施例。 存储单元包括在衬底中形成的第一和第二扩散区之间延伸的沟道区。 在沟道区上形成隧道介电材料。 在隧道电介质材料上形成存储介质以存储电荷。 存储介质设置在第一界面材料和第二界面材料之间，每个界面材料在存储介质和周围介质材料之间提供更平滑的界面。 在存储介质上形成电荷阻挡材料，随后形成控制栅极材料。

    Methods of forming reverse mode non-volatile memory cell structures
    2.
    发明授权
    Methods of forming reverse mode non-volatile memory cell structures 有权
    形成反向模式非易失性存储单元结构的方法

    公开(公告)号：US08802526B2

    公开(公告)日：2014-08-12

    申请号：US13409832

    申请日：2012-03-01

    申请人： Arup Bhattacharyya

    发明人： Arup Bhattacharyya

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S438/954

    摘要： Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

    摘要翻译： 描述了形成非易失性存储单元结构的方法，其有助于在反向和正常模式浮动节点存储器单元中使用具有不对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和擦除，同时保持高电荷阻挡屏障 和深载体捕获位点保持良好的电荷。 低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。 低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。 这样的存储器单元还允许多个位存储。 这些特性允许这样的存储器单元在通用存储器的定义内操作，能够替换系统中的DRAM和ROM。

    Scalable multi-functional and multi-level nano-crystal non-volatile memory device
    4.
    发明授权
    Scalable multi-functional and multi-level nano-crystal non-volatile memory device 有权
    可扩展的多功能和多级纳米晶体非易失性存储器件

    公开(公告)号：US08530951B2

    公开(公告)日：2013-09-10

    申请号：US13608483

    申请日：2012-09-10

    申请人： Arup Bhattacharyya

    发明人： Arup Bhattacharyya

    IPC分类号： H01L29/76 ,  G11C16/04

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  G11C16/10 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/513

    摘要： A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

    摘要翻译： 多功能和多层存储单元包括在衬底上形成的隧道层。 在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。 在隧道层上形成电荷阻挡层。 在一个实施方案中，该层由HfSiON形成。 控制栅极形成在电荷阻挡层上。 离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。 离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。 离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

    SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE
    7.
    发明申请
    SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE 有权
    可扩展的多功能和多级纳米晶体非易失性存储器件

    公开(公告)号：US20130003456A1

    公开(公告)日：2013-01-03

    申请号：US13608483

    申请日：2012-09-10

    申请人： Arup Bhattacharyya

    发明人： Arup Bhattacharyya

    IPC分类号： G11C16/10

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  G11C16/10 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/513

    摘要： A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embodiment, this layer is formed from HfSiON. A control gate is formed over the charge blocking layer. A discrete trapping layer is embedded in either the tunnel layer or the charge blocking layer, depending on the desired level of non-volatility. The closer the discrete trapping layer is formed to the substrate/insulator interface, the lower the non-volatility of the device. The discrete trapping layer is formed from nano-crystals having a uniform size and distribution.

    摘要翻译： 多功能和多层存储单元包括在衬底上形成的隧道层。 在一个实施例中，隧道层包括两层，例如HfO 2和LaAlO 3。 在隧道层上形成电荷阻挡层。 在一个实施方案中，该层由HfSiON形成。 控制栅极形成在电荷阻挡层上。 离散的捕获层嵌入在隧道层或电荷阻挡层中，这取决于期望的非挥发性水平。 离散捕获层越靠近衬底/绝缘体界面，器件的非易失性越低。 离散捕获层由具有均匀尺寸和分布的纳米晶体形成。

    Solar cell systems
    8.
    发明授权
    Solar cell systems 失效
    太阳能电池系统

    公开(公告)号：US08319272B2

    公开(公告)日：2012-11-27

    申请号：US12757870

    申请日：2010-04-09

    申请人： Arup Bhattacharyya

    发明人： Arup Bhattacharyya

    IPC分类号： H01L29/388 ,  H01L31/042

    CPC分类号： H01L31/022425 ,  H01L31/0264 ,  H01L31/062 ,  H01L31/0725 ,  H01L31/1085 ,  Y02E10/50

    摘要： The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.

    摘要翻译： 本发明包括含有一层或多层半导体富集绝缘体（富含富硅的绝缘体为富硅氧化硅和富含硅的氮化硅）的光电器件，并且包括含有一层或多层半导体富集绝缘体的太阳能电池 。 本发明还包括形成光电器件和太阳能电池的方法。

    Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset
    9.
    发明授权
    Methods of forming non-volatile memory having tunnel insulator of increasing conduction band offset 有权
    形成具有增加导带偏移的隧道绝缘体的非易失性存储器的方法

    公开(公告)号：US08129243B2

    公开(公告)日：2012-03-06

    申请号：US12247608

    申请日：2008-10-08

    申请人： Arup Bhattacharyya

    发明人： Arup Bhattacharyya

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  B82Y10/00 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  Y10S438/954

    摘要： Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

    摘要翻译： 描述了形成非易失性存储单元结构的方法，其有助于在反向和正常模式浮动节点存储器单元中使用具有不对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和擦除，同时保持高电荷阻挡屏障 和深载体捕获位点保持良好的电荷。 低电压直接隧道编程和擦除能力降低了高能量载流子对栅极堆叠和晶格的损害，减少了写入疲劳和增强了器件寿命。 低电压直接隧道编程和擦除功能还可以通过低电压设计和进一步的器件特性缩放来缩小尺寸。 这样的存储器单元还允许多个位存储。 这些特性允许这样的存储器单元在通用存储器的定义内操作，能够替换系统中的DRAM和ROM。