公开(公告)号：US20050158924A1

公开(公告)日：2005-07-21

申请号：US10707878

申请日：2004-01-20

申请人： Ashima Chakravarti ,  Bruce Doris ,  Romany Ghali ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Woo-Hyeong Lee ,  Anita Madan

发明人： Ashima Chakravarti ,  Bruce Doris ,  Romany Ghali ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Woo-Hyeong Lee ,  Anita Madan

IPC分类号： C23C16/24 ,  C23C16/46 ,  H01L21/00 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： C23C16/24 ,  C23C16/46 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4925

摘要： A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.

摘要翻译： 形成超小晶粒尺寸的多晶硅的方法采用CVD装置的衬底的上侧和下侧的差分加热，其中衬底的下侧比上侧受到明显更多的功率，优选大于 75％的权力; 并且其中在超过550℃的硅结晶温度超过50℃的温度下在沉积期间保持基底。

公开(公告)号：US06576565B1

公开(公告)日：2003-06-10

申请号：US10075152

申请日：2002-02-14

申请人： Ashima Chakravarti ,  Oleg Gluschenkov ,  Irene Lennox McStay

发明人： Ashima Chakravarti ,  Oleg Gluschenkov ,  Irene Lennox McStay

IPC分类号： H01L2131

CPC分类号： C23C16/45572 ,  C23C16/045 ,  C23C16/481 ,  C23C16/52 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/67109 ,  H01L21/67115 ,  H01L27/10861

摘要： An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.

摘要翻译： 一种用于在具有非平面结构（114）的半导体晶片上沉积材料的装置（110）和方法。 晶片（114）定位在室（111）中，反应气体（132）被引入室（111）中。 加热气体（132）和晶片（114），其中处理室（111）中和晶片（114）表面附近的气体（132）温度低于晶片（114）表面的温度 。 使用化学气相沉积将材料沉积在晶片（114）表面上。 当加热晶片（114）时，气体冷却器可用于降低反应气体（132）的温度。

公开(公告)号：US20090146181A1

公开(公告)日：2009-06-11

申请号：US11952939

申请日：2007-12-07

申请人： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

发明人： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

摘要翻译： 一种集成电路系统，包括：提供包括掺杂外延层的PFET器件; 以及通过使用能量源从掺杂的外延层扩散掺杂剂形成源极/漏极扩展。

公开(公告)号：US20070238267A1

公开(公告)日：2007-10-11

申请号：US11308463

申请日：2006-03-28

申请人： Yaocheng Liu ,  Oleg Gluschenkov ,  Anita Madan ,  Kern Rim ,  Judson Holt

发明人： Yaocheng Liu ,  Oleg Gluschenkov ,  Anita Madan ,  Kern Rim ,  Judson Holt

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02667 ,  H01L21/02524 ,  H01L21/2022 ,  H01L21/2026 ,  H01L21/268 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

摘要： Expitaxial substitutional solid solutions of silicon carbon can be obtained by an ultrafast anneal of an amorphous carbon-containing silicon material. The anneal is performed at a temperature above the recrystallization point, but below the melting point of the material and preferably lasts for less than 100 milliseconds in this temperature regime. The anneal is preferably a flash anneal or laser anneal. This approach is able to produce epitaxial silicon and carbon-containing materials with a substantial portion of the carbon atoms at substitutional lattice positions. The approach is especially useful in CMOS processes and other electronic device manufacture where the presence of epitaxial Si1−yCy, y

摘要翻译： 可以通过非晶态含碳硅材料的超快速退火获得硅碳的外延取代固溶体。 退火在高于再结晶点的温度下进行，但低于材料的熔点，并且在该温度范围内优选持续小于100毫秒。 退火优选是闪光退火或激光退火。 这种方法能够产生具有相当大部分碳原子在取代晶格位置的外延硅和含碳材料。 该方法在CMOS工艺和其它电子器件制造中特别有用，其中外延Si 1-y C y y y的存在y <0.1对于应变工程或带隙工程是理想的 。

公开(公告)号：US20070262348A1

公开(公告)日：2007-11-15

申请号：US11782351

申请日：2007-07-24

申请人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

发明人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

IPC分类号： H01L21/3205 ,  H01L29/73

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

公开(公告)号：US20050282341A1

公开(公告)日：2005-12-22

申请号：US10869658

申请日：2004-06-16

申请人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

发明人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

公开(公告)号：US20070063278A1

公开(公告)日：2007-03-22

申请号：US11162780

申请日：2005-09-22

申请人： Bruce Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

发明人： Bruce Doris ,  Gregory Costrini ,  Oleg Gluschenkov ,  Meikei Ieong ,  Nakgeuon Seong

IPC分类号： H01L27/12

CPC分类号： H01L27/1104 ,  H01L27/11 ,  Y10S257/903 ,  Y10S438/973

摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.

摘要翻译： 本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。 这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。 下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。 衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。 更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于 传输栅晶体管。

公开(公告)号：US20050194699A1

公开(公告)日：2005-09-08

申请号：US10708430

申请日：2004-03-03

申请人： Michael Belyansky ,  Bruce Doris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Bruce Doris ,  Oleg Gluschenkov

IPC分类号： H01L27/088

CPC分类号： H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

摘要翻译： 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。

公开(公告)号：US20080090366A1

公开(公告)日：2008-04-17

申请号：US11870436

申请日：2007-10-11

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US20060289909A1

公开(公告)日：2006-12-28

申请号：US11514605

申请日：2006-09-01

申请人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

发明人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

IPC分类号： H01L29/76

CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区域，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。