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1.发明授权公开(公告)号：US10396808B2
公开(公告)日：2019-08-27
申请号：US16084997
申请日：2017-03-15
发明人： Nan Sun
摘要： The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.
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公开(公告)号：US20210384874A1
公开(公告)日：2021-12-09
申请号：US17339592
申请日：2021-06-04
发明人： Nan Sun , Xiyuan Tang
摘要： An exemplary system and method is disclosed employing a floating inverter amplifier comprising an inverter-based circuit comprising an input configured to be switchable between a floating reservoir capacitor during a first phase of operation and to a device power source during a second phase of operation. In some embodiments, the floating inverter amplifier is further configured for current reuse and dynamic bias. In other embodiments, the floating inverter amplifier is further configured with a dynamic cascode mechanism that does not need any additional bias voltage. The dynamic cascode mechanism may be used in combination with 2-step fast-settling operation to provide high-gain and high-speed noise suppression operation.
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公开(公告)号：US10284145B2
公开(公告)日：2019-05-07
申请号：US15803081
申请日：2017-11-03
发明人： Nan Sun , Miguel Gandara
IPC分类号： H03M1/12 , H03F1/02 , H03F1/08 , H03F3/45 , H03K3/356 , H03M1/06 , H03M1/14 , H03M1/10 , H03M1/00
摘要： A variable gain amplifier utilizing positive feedback and time-domain calibration includes an integration phase and a regeneration phase. A current source provides a bias current that increases linearity in the integration phase and reduces common-mode voltage dependence. The circuit includes a timing control loop, wherein a variable gain of a residue amplifier is proportional to a first time that a timing control loop signal is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase. A strong-arm latch structure acts as a positive feedback latch until the first time is de-asserted.
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公开(公告)号：US11539336B2
公开(公告)日：2022-12-27
申请号：US17339592
申请日：2021-06-04
发明人： Nan Sun , Xiyuan Tang
摘要： An exemplary system and method is disclosed employing a floating inverter amplifier comprising an inverter-based circuit comprising an input configured to be switchable between a floating reservoir capacitor during a first phase of operation and to a device power source during a second phase of operation. In some embodiments, the floating inverter amplifier is further configured for current reuse and dynamic bias. In other embodiments, the floating inverter amplifier is further configured with a dynamic cascode mechanism that does not need any additional bias voltage. The dynamic cascode mechanism may be used in combination with 2-step fast-settling operation to provide high-gain and high-speed noise suppression operation.
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5.发明申请公开(公告)号：US20190074842A1
公开(公告)日：2019-03-07
申请号：US16084997
申请日：2017-03-15
发明人： Nan Sun
CPC分类号： H03L7/1974 , H03L7/06 , H03L7/089 , H03L7/091 , H03L7/093 , H03L7/18 , H03L7/197 , H03L2207/50
摘要： The exemplified technology provides a circuit and clock synthesis technique that suppresses quantization noise in a ΔΣ fractional-N phase-locked loop (PLL) using a fineresolution multi-element fractional divider. The circuit and clock synthesis method beneficially suppresses noise uniformly over the entire frequency range. The circuit can be implemented using mostly digital circuitry, and is applicable for use with both analog and digital PLLs. With an 8-element fractional divider, it is observed that the circuit and clock synthesis technique can suppress quantization noise while incurring only a small increase in hardware complexity.
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公开(公告)号：US20180309408A1
公开(公告)日：2018-10-25
申请号：US15803081
申请日：2017-11-03
发明人： Nan Sun , Miguel Gandara
CPC分类号： H03F1/0211 , H03F1/08 , H03F1/086 , H03F1/3211 , H03F1/38 , H03F3/45179 , H03F3/45188 , H03F3/45475 , H03F3/45632 , H03F3/45928 , H03F2203/45048 , H03F2203/45551 , H03F2203/45634 , H03K3/35613 , H03M1/00 , H03M1/06 , H03M1/10 , H03M1/12 , H03M1/14
摘要： A variable gain amplifier utilizing positive feedback and time-domain calibration includes an integration phase and a regeneration phase. A current source provides a bias current that increases linearity in the integration phase and reduces common-mode voltage dependence. The circuit includes a timing control loop, wherein a variable gain of a residue amplifier is proportional to a first time that a timing control loop signal is kept high, as determined by an on or off status of respectively paired inverter assemblies each having an input voltage determined by an amplifier output voltage during the regeneration phase. A strong-arm latch structure acts as a positive feedback latch until the first time is de-asserted.
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公开(公告)号：US20170093414A1
公开(公告)日：2017-03-30
申请号：US15278519
申请日：2016-09-28
发明人： Nan Sun , Long Chen , Xiyuan Tang
CPC分类号： H03M1/08 , H03M1/04 , H03M1/0697 , H03M1/1009 , H03M1/38 , H03M1/468
摘要： Disclosed herein are systems and methods that describe statistical estimation based noise reduction for SAR ADCs. For SAR ADCs, the conversion error can be available at the comparator input. Although a noisy 1-bit comparator may not be able to produce an accurate estimation for its input if used only once, the comparison can be repeated multiple times for a designated bit of the multi-bit SAR ADC. This can allow for the improvement of the estimation accuracy by examining the probability of the comparator output being “1” or “0”. The estimation of a signal from a noisy environment using multiple trials can be cast as a classic statistical estimation issue. In one aspect of the disclosure, an optimal Bayes estimator is disclosed to achieve a low estimation error from the comparator on a designated bit of the multi-bit SAR ADC.
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公开(公告)号：US11569826B2
公开(公告)日：2023-01-31
申请号：US17176341
申请日：2021-02-16
发明人： Xiyuan Tang , Nan Sun
摘要： An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.
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公开(公告)号：US11223335B2
公开(公告)日：2022-01-11
申请号：US16614625
申请日：2018-06-04
发明人： Nan Sun , Linxiao Shen
摘要： The exemplified disclosure presents a highly power efficient amplifier (e.g., front-end inverter and/or amplifier) that achieves significant current reuse (e.g., 6-time for a 3-stack embodiments) by stacking inverters and splitting the capacitor feedback network. In some embodiments, the exemplified technology facilitates N-time current reuse to substantially reduced power consumption. It is observed that the exemplified disclosure facilitates significant current-reuse operation that significantly boost gain gm while providing low noise performance without increasing power usage. In addition, the exemplified technology is implemented such that current reuse and number of transistor has a generally linear relationship and using fewer transistors as compared to known circuits of similar topology.
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公开(公告)号：US20170126239A1
公开(公告)日：2017-05-04
申请号：US15343446
申请日：2016-11-04
发明人： Nan Sun , Wenjuan Guo
摘要： Disclosed herein are systems and methods that describe a noise-shaping (NS) SAR architecture that can be simple, effective, and low power. In an aspect, a method includes the operation of receiving a first analog input; determining a first digital output based on the first analog input; obtaining a first quantization error for the first digital output; integrating the first quantization error; receiving a second analog input; and determining a second digital output based on the summation of the second analog input and the first integrated quantization error to perform noise-shaping.
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