公开(公告)号：US4897364A

公开(公告)日：1990-01-30

申请号：US315866

申请日：1989-02-27

申请人： Bich-Yen Nguyen ,  Philip J. Tobin ,  Shih-Wei Sun ,  Michael Woo

发明人： Bich-Yen Nguyen ,  Philip J. Tobin ,  Shih-Wei Sun ,  Michael Woo

IPC分类号： H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76216

摘要： An improved LOCOS device isolation method for forming a field oxide is disclosed having the advantage of controllable and uniform sidewall framing of a nutride oxidation mask. This advantage is achieved by the use of a polysilicon layer overlying a nitride mask with the polysilicon providing an etching endpoint during the anisotropic etching used for sidewall formation. In one embodiment of the invention a silicon substrate is provided having a pad oxide formed on its surface and a first polysilicon stress-relief buffer layer formed overlying the pad oxide. A first nitride layer, to be used for oxidation masking during field oxide growth, is deposited overlying the first polysilicon layer. Next, a second polysilicon, etch-resistant buffer layer is deposited overlying the first nitride layer.The first nitride layer and second polysilicon layer are patterned by conventional lithography while the first polysilicon and pad oxide layers remained unpatterned. A second nitride layer is deposited overlying the patterned second polysilicon layer and exposed regions of the first polysilicon layer. Sidewalls are formed on the edges of the patterned first nitride and second polysilicon layers by anisotropically etching the second nitride layer using the first and second polysilicon layers as etching endpoints. Finally, the field oxide is grown by conventional methods. The grown field oxide exhibits reduced bird's beak length, and the resulting field separation is not limited by optical lithography resolution.

摘要翻译： 公开了一种用于形成场氧化物的改进的LOCOS器件隔离方法，其具有可控制和均匀的叶片氧化掩模侧壁框架的优点。 该优点通过使用覆盖氮化物掩模的多晶硅层来实现，其中多晶硅在用于侧壁形成的各向异性蚀刻期间提供蚀刻终点。 在本发明的一个实施例中，提供硅衬底，其具有在其表面上形成的衬垫氧化物和形成在衬垫氧化物上的第一多晶硅应力释放缓冲层。 在场氧化物生长期间用于氧化掩蔽的第一氮化物层沉积在第一多晶硅层上。 接下来，沉积覆盖第一氮化物层的第二多晶硅，耐蚀刻缓冲层。 第一氮化物层和第二多晶硅层通过常规光刻图案化，而第一多晶硅和衬垫氧化物层保持未图案化。 第二氮化物层沉积在图案化的第二多晶硅层和第一多晶硅层的暴露区域上。 通过使用第一和第二多晶硅层作为蚀刻终点通过各向异性蚀刻第二氮化物层，在图案化的第一氮化物和第二多晶硅层的边缘上形成侧壁。 最后，通过常规方法生长场氧化物。 生长的田间氧化物表现出减少的鸟的喙长度，并且所得到的场分离不受光学光刻分辨率的限制。

公开(公告)号：US20050003671A1

公开(公告)日：2005-01-06

申请号：US10902315

申请日：2004-07-29

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  W.B. Shieh ,  J.Y. Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  W.B. Shieh ,  J.Y. Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/027 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。 第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。 防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。 可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

公开(公告)号：US06238972B1

公开(公告)日：2001-05-29

申请号：US09096351

申请日：1998-06-12

申请人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L28/84

摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.

摘要翻译： 通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si） 的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。 在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新沉积以在电极的表面上提供第二层HSG-Si。 如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。 在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。 在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。 该纹理硅结构形成DRAM电容器的下电极。

公开(公告)号：US06198617B1

公开(公告)日：2001-03-06

申请号：US09228853

申请日：1999-01-12

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01G430

CPC分类号： H01L28/55 ,  H01L21/76838 ,  H01L27/0805

摘要： A structure of a capacitor includes an electromigration layer, which is located on a dielectric layer and serves as a lower electrode of the capacitor. A pattered capacitor dielectric layer is located on the electromigration layer, and a patterned metallic layer is located on the capacitor dielectric layer and serves as an upper electrode of the capacitor.

摘要翻译： 电容器的结构包括位于电介质层上并用作电容器的下电极的电迁移层。 图案化的电容器电介质层位于电迁移层上，并且图案化的金属层位于电容器介电层上并用作电容器的上电极。

公开(公告)号：US5936286A

公开(公告)日：1999-08-10

申请号：US806346

申请日：1997-02-26

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/823456 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/42368 ,  Y10S257/903 ,  Y10S257/904

摘要： An SRAM cell having improved stability includes pass transistors having gate electrodes which are shaped by oxidation so that the lower edges of the gate electrodes are raised away from the substrate surface. Because the gate electrodes of the load and pull-down transistors are masked during the oxidation process, the gate electrodes of the load and pull-down transistors have the conventional rectangular shape. The modified shape of the gate electrodes of the pass transistors decreases the current flowing through the pass transistors relative to that which flows through the pull-down transistors, reducing the likelihood that data can inadvertently be lost from the SRAM cell.

公开(公告)号：US5899742A

公开(公告)日：1999-05-04

申请号：US35347

申请日：1998-03-05

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  Y10S148/019

摘要： The invention provides a novel method, in which self-aligned, borderless contacts and local interconnections of semiconductor devices are manufactured in an integral process. The method is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. That is, this invention provides a self-aligned local-interconnect and contact (SALIC) method for a logic technology to forming the self-aligned, borderless contacts, and local interconnects (LI) simultaneously.

摘要翻译： 本发明提供了一种新颖的方法，其中半导体器件的自对准，无边界接触和局部互连以整体工艺制造。 该方法与LOGIC自对准硅化钛（SALICIDE）和N + / P +多重双栅极工艺模块兼容。 也就是说，本发明提供了一种用于逻辑技术的自对准局部互连和接触（SALIC）方法，以同时形成自对准无边界触点和局部互连（LI）。

公开(公告)号：US5886375A

公开(公告)日：1999-03-23

申请号：US735007

申请日：1996-10-22

申请人： Shih-Wei Sun

发明人： Shih-Wei Sun

IPC分类号： H01L27/11 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/1108 ,  Y10S257/903

摘要： An SRAM cell having improved soft error immunity connects each of the storage nodes of the SRAM cell to an overlying electrode having a textured surface which is separated from a constant potential plate electrode by a dielectric layer. The textured surface of the overlying electrode may be created by forming hemispherical-grained silicon on its surface, or by forming a fin structure on its surface. The textured surface of the overlying electrode provides increased capacitance between the overlying electrode and the constant potential plate electrode, thereby increasing the capacitance of the storage node.

摘要翻译： 具有改进的软错误抗扰性的SRAM单元将SRAM单元的每个存储节点连接到具有通过介电层与恒定电位板电极分离的纹理表面的上覆电极。 上覆电极的纹理表面可以通过在其表面上形成半球形硅，或者通过在其表面上形成翅片结构来产生。 上覆电极的纹理表面在上覆电极和恒电位平板电极之间提供增加的电容，从而增加存储节点的电容。

公开(公告)号：US5864163A

公开(公告)日：1999-01-26

申请号：US751238

申请日：1996-11-18

申请人： Jih-Wen Chou ,  Shih-Wei Sun

发明人： Jih-Wen Chou ,  Shih-Wei Sun

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7838 ,  H01L21/26513 ,  H01L21/8238 ,  H01L21/823807 ,  H01L27/0927 ,  H01L29/66477

摘要： The channel doping profile of a PMOS field effect transistor consists of a shallow distribution of a P-type dopant as a threshold adjust implant, a deeper distribution of an N-type dopant as an buried channel stop implant and a still deeper implantation of an N-type dopant as an antipunchthrough implant. A junction is formed between the P-type threshold adjust implant and the N-type buried channel stop implant at a relatively shallow depth so that the depth of the buried channel region is limited by the buried channel stop implant, reducing the short channel effect. The channel doping profile is formed so that diffusion of impurities from the channel region to the gate oxide is prevented. The buried channel stop implant is made first through a sacrificial oxide layer. The sacrificial oxide is etched and a gate oxide layer and a thin film of polysilicon are deposited on the surface of the gate oxide. Both the threshold implant and the antipunchthrough implant are made through the thin polysilicon layer and the gate oxide layer. After the channel doping profile is defined, additional gate material is deposited and device construction is completed in the normal manner.

摘要翻译： PMOS场效应晶体管的沟道掺杂分布由P型掺杂剂的浅分布组成，作为阈值调整注入，作为掩埋沟道停止注入的N型掺杂剂的深度分布以及N 型掺杂剂作为抗穿通植入物。 在P型阈值调整植入物和N型埋入通道停止植入物之间形成一个相对较浅深度的结，使得掩埋沟道区域的深度受到掩埋沟道阻挡植入物的限制，从而减少短沟道效应。 形成沟道掺杂分布，从而防止杂质从沟道区扩散到栅极氧化物。 首先通过牺牲氧化物层制造掩埋沟道阻挡植入物。 蚀刻牺牲氧化物，并且栅极氧化物层和多晶硅薄膜沉积在栅极氧化物的表面上。 通过薄多晶硅层和栅极氧化物层制造阈值植入和抗穿通植入物两者。 在限定沟道掺杂分布之后，沉积额外的栅极材料并以正常方式完成器件结构。

公开(公告)号：US5780348A

公开(公告)日：1998-07-14

申请号：US892314

申请日：1997-07-14

申请人： Tony Lin ,  Water Lur ,  Shih-Wei Sun

发明人： Tony Lin ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/336 ,  H01L21/283

CPC分类号： H01L29/6659 ,  H01L29/665

摘要： A method of making a self-aligned silicide component having parasitic spacers formed on the sides of an upper surface of the component isolating regions, the bottom sides of the spacers and the exposed sides of the gate regions, which increases a distance from a metal silicide layer at a corner of an active region neighboring the component isolating region to the source/drain junction, to prevent undesired current leakages. The formation of parasitic spacers increases a distance from the metal silicide layer lying above the gate surface to the metal silicide layer lying above the source/drain surface so that an ability to withstand electrostatic damages is enhanced.

摘要翻译： 一种制造具有寄生间隔物的自对准硅化物组分的方法，其形成在部件隔离区域的上表面的侧面上，间隔物的底侧和栅极区域的暴露侧，其增加了距金属硅化物的距离 在与源极/漏极结的部件隔离区域相邻的有源区域的拐角处的层，以防止不期望的电流泄漏。 寄生间隔物的形成增加了位于栅极表面上方的金属硅化物层到位于源极/漏极表面上方的金属硅化物层的距离，从而增强了承受静电损伤的能力。

公开(公告)号：US5733794A

公开(公告)日：1998-03-31

申请号：US384177

申请日：1995-02-06

申请人： Percy Veryon Gilbert ,  Paul G. Y. Tsui ,  Shih-Wei Sun ,  Stephen G. Jamison

发明人： Percy Veryon Gilbert ,  Paul G. Y. Tsui ,  Shih-Wei Sun ,  Stephen G. Jamison

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088 ,  H01L21/265

CPC分类号： H01L27/0266

摘要： A semiconductor device with an electrostatic discharge (ESD) protection transistor is devised, wherein the ESD protection transistor has halo regions of an opposite conductivity type from the source and drain regions adjacent thereto. In one embodiment, the ESD protection transistor is a thick field oxide (TFO) transistor. In some cases, the halo regions may be provided with an ion implant step without the use of an extra mask. The halo regions permit the ESD protection transistor to have its breakdown voltage adjusted so that it turns on before the device it is protecting is affected by an ESD event. The use of halo regions avoids the increase in device area and adverse effects to the AC performance of the circuit being protected that are disadvantages of prior approaches.

摘要翻译： 设计了具有静电放电（ESD）保护晶体管的半导体器件，其中ESD保护晶体管具有与其相邻的源极和漏极区域具有相反导电类型的晕圈。 在一个实施例中，ESD保护晶体管是厚场氧化物（TFO）晶体管。 在一些情况下，可以在不使用额外掩模的情况下为晕区提供离子注入步骤。 光晕区域允许ESD保护晶体管调整其击穿电压，使其在保护器件受ESD事件影响之前导通。 晕圈的使用避免了设备面积的增加和对被保护电路的AC性能的不利影响，这是现有方法的缺点。