公开(公告)号：US20050064636A1

公开(公告)日：2005-03-24

申请号：US10669898

申请日：2003-09-24

申请人： Cyril Cabral ,  Meikei Ieong ,  Jakub Kedzierski

发明人： Cyril Cabral ,  Meikei Ieong ,  Jakub Kedzierski

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/338

CPC分类号： H01L29/66628 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835

摘要： A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.

摘要翻译： 制造互补金属氧化物半导体（CMOS）场效应晶体管的方法，其包括选择性掺杂和包括晶体管的栅电极的多晶硅材料的全硅化。 在一个实施方案中，在硅化之前，多晶硅是非晶化的。 在另一个实施方案中，在低的衬底温度下进行硅化。

公开(公告)号：US20050118757A1

公开(公告)日：2005-06-02

申请号：US10725851

申请日：2003-12-02

申请人： Cyril Cabral ,  Jakub Kedzierski ,  Victor Ku ,  Christian Lavoie ,  Vijay Narayanan ,  An Steegen

发明人： Cyril Cabral ,  Jakub Kedzierski ,  Victor Ku ,  Christian Lavoie ,  Vijay Narayanan ,  An Steegen

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823835

摘要： A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.

摘要翻译： 提供了允许使用自对准工艺（自对准硅化物）以及一个或多个光刻步骤并入硅化物触点（S / D和栅极）和金属硅化物栅极的CMOS硅化物金属集成方案。 本发明的集成方案最小化了制造包含硅化物触点和硅化物栅极金属的CMOS结构所涉及的复杂性和成本。

公开(公告)号：US20060189061A1

公开(公告)日：2006-08-24

申请号：US11407313

申请日：2006-04-19

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20050186747A1

公开(公告)日：2005-08-25

申请号：US10786901

申请日：2004-02-25

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20070034967A1

公开(公告)日：2007-02-15

申请号：US11537718

申请日：2006-10-02

申请人： Hasan Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub Kedzierski ,  Cyril Cabral

发明人： Hasan Nayfeh ,  Mahender Kumar ,  Sunfei Fang ,  Jakub Kedzierski ,  Cyril Cabral

IPC分类号： H01L29/94

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.

摘要翻译： 描述了MOSFET结构和形成方法。 该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换为半导体金属合金 MOSFET类型区域。 在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。 在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。

公开(公告)号：US20050106788A1

公开(公告)日：2005-05-19

申请号：US11001913

申请日：2004-12-02

申请人： Ricky Amos ,  Katayun Barmak ,  Diane Boyd ,  Cyril Cabral ,  Meikei Leong ,  Thomas Kanarsky ,  Jakub Kedzierski

发明人： Ricky Amos ,  Katayun Barmak ,  Diane Boyd ,  Cyril Cabral ,  Meikei Leong ,  Thomas Kanarsky ,  Jakub Kedzierski

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L31/0392

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/66545

摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

公开(公告)号：US20080142894A1

公开(公告)日：2008-06-19

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L27/088 ,  H01L29/423

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20060264048A1

公开(公告)日：2006-11-23

申请号：US11461220

申请日：2006-07-31

申请人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

发明人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。

公开(公告)号：US20060081885A1

公开(公告)日：2006-04-20

申请号：US11228269

申请日：2005-10-26

申请人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

发明人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些镀层材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20060051961A1

公开(公告)日：2006-03-09

申请号：US10935497

申请日：2004-09-07

申请人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

发明人： Cyril Cabral ,  Michael Cobb ,  Balasubramanian Pranatharthi Haran ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Andrew Mansson ,  Horatio Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step. A selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

摘要翻译： 本发明提供一种形成自对准Ni合金硅化物接触的方法。 本发明的方法首先首先用Pt和任选的以下金属Pd，Rh，Ti，V，Cr，Zr，Nb，Mo，Hf，Ta，W或Re中的至少一种沉积导电Ni合金， 整个半导体结构，其包括至少一个栅极堆叠区域。 包含例如Ti，TiN或W的氧扩散阻挡层沉积在结构上以防止金属的氧化。 然后使用退火步骤在金属与硅接触的区域中形成NiSi，PtSi接触。 与诸如SiO 2和Si 3 N 4 N之类的绝缘材料直接接触的金属在金属合金硅化物接触期间不会转化为金属合金硅化物接触 退火步骤。 然后执行选择性蚀刻步骤以从间隔物和沟槽隔离区域的侧壁去除未反应的金属。