公开(公告)号：US20130075908A1

公开(公告)日：2013-03-28

申请号：US13246904

申请日：2011-09-28

申请人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

发明人： Cyril Cabral, JR. ,  Geraud Jean-Michel Dubois ,  Daniel C. Edelstein ,  Takeshi Nogami ,  Daniel P. Sanders

IPC分类号： H01L23/482 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method for fabricating the interconnect structure having enhanced performance and reliability, by minimizing oxygen intrusion into a seed layer and an electroplated copper layer of the interconnect structure, are disclosed. At least one opening in a dielectric layer is formed. A sacrificial oxidation layer disposed on the dielectric layer is formed. The sacrificial oxidation layer minimizes oxygen intrusion into the seed layer and the electroplated copper layer of the interconnect structure. A barrier metal layer disposed on the sacrificial oxidation layer is formed. A seed layer disposed on the barrier metal layer is formed. An electroplated copper layer disposed on the seed layer is formed. A planarized surface is formed, wherein a portion of the sacrificial oxidation layer, the barrier metal layer, the seed layer, and the electroplated copper layer are removed. In addition, a capping layer disposed on the planarized surface is formed.

摘要翻译： 公开了一种用于制造具有增强的性能和可靠性的互连结构的互连结构和方法，通过最小化氧侵入种子层和互连结构的电镀铜层。 形成电介质层中的至少一个开口。 形成设置在电介质层上的牺牲氧化层。 牺牲氧化层使氧侵入种子层和互连结构的电镀铜层最小化。 形成设置在牺牲氧化层上的阻挡金属层。 形成设置在阻挡金属层上的籽晶层。 形成设置在种子层上的电镀铜层。 形成平坦化表面，其中除去部分牺牲氧化层，阻挡金属层，种子层和电镀铜层。 此外，形成设置在平坦化表面上的覆盖层。

公开(公告)号：US20130040454A1

公开(公告)日：2013-02-14

申请号：US13205063

申请日：2011-08-08

申请人： Cyril Cabral, JR. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P. Rodbell

IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/302

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76828 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

摘要翻译： 提供了一种通过退火工艺改性硅基技术的化学或微结构的方法。 该方法包括将反应性材料层沉积在选定的互连附近，点燃反应性材料层，以及通过从点燃的反应性材料层传递的热量使互连件退火。 该方法还可以结合硅化物/硅界面以及硅基技术的区域来实现。

公开(公告)号：US08362600B2

公开(公告)日：2013-01-29

申请号：US12689268

申请日：2010-01-19

申请人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  David F. Heidel ,  Conal Eugene Murray ,  Kenneth Parker Rodbell ,  Henry Hong Ki Tang

发明人： Cyril Cabral, Jr. ,  Michael S. Gordon ,  David F. Heidel ,  Conal Eugene Murray ,  Kenneth Parker Rodbell ,  Henry Hong Ki Tang

IPC分类号： H01L23/556 ,  H01L21/60

CPC分类号： H01L23/556 ,  H01L24/13 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00

摘要： A method is disclosed that includes providing a semiconductor substrate having one or more device levels including a number of devices, and forming a number of wiring levels on a top surface of the one or more device levels, wherein one or more of the number of wiring levels includes one or more alpha particle blocking shields situated between at least one of the number of devices and a predetermined first location where a terminal pad will be formed in one of the wiring levels, the one or more alpha particle blocking shields placed at a second location, having one or more widths, and occupying a predetermined number of the wiring levels, sufficient to prevent a predetermined percentage of alpha particles of a selected energy or less expected to be emitted from an alpha particle emitting metallization to be formed adjacent and connected to the terminal pad from reaching the one device.

摘要翻译： 公开了一种方法，其包括提供具有包括多个器件的一个或多个器件电平的半导体衬底，以及在所述一个或多个器件级的顶表面上形成多个布线电平，其中所述多个布线中的一个或多个 水平包括一个或多个α粒子阻挡屏蔽，位于多个器件中的至少一个与预定的第一位置之间，其中端子焊盘将形成在一个布线层中，一个或多个α粒子阻挡屏蔽放置在第二个 位置，具有一个或多个宽度并且占据预定数量的布线水平，足以防止预定百分比的α粒子被选择的能量或预期从发射的α粒子发射的金属化物发射出来邻近并连接到 终端垫到达一个设备。

公开(公告)号：US20120267768A1

公开(公告)日：2012-10-25

申请号：US13533182

申请日：2012-06-26

申请人： Paul Stephen Andry ,  Cyril Cabral, JR. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

发明人： Paul Stephen Andry ,  Cyril Cabral, JR. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC分类号： H01L23/556 ,  B23K3/00

CPC分类号： H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

摘要： A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

摘要翻译： 用于形成结构的结构和系统。 该结构包括半导体芯片和具有顶侧和底侧的插入屏蔽。 半导体芯片包括N个芯片电极焊盘，其中N是至少为2的正整数。N个芯片电极焊盘与半导体芯片上的多个器件电连接。 电气屏蔽包括2N个导电体和N个屏蔽电极垫。 每个屏蔽电焊垫与2N电导体的相应电导体电接触并直接物理接触。 中间屏蔽包括屏蔽材料。 屏蔽材料包括第一半导体材料。 半导体芯片被结合到插入式屏蔽的顶侧。 每个芯片电焊盘与N个屏蔽电焊盘的相应屏蔽电焊垫电接触并直接物理接触。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US08129267B2

公开(公告)日：2012-03-06

申请号：US12052881

申请日：2008-03-21

申请人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

发明人： Cyril Cabral, Jr. ,  K. Paul Muller ,  Kenneth P. Rodbell

IPC分类号： H01L21/4763

CPC分类号： H01L23/5223 ,  H01L23/3192 ,  H01L23/53238 ,  H01L23/556 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02166 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/10125 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13007 ,  H01L2224/13028 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13487 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/05552 ,  H01L2924/00

摘要： An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

摘要翻译： 一种α粒子阻挡结构及其制造方法。 该结构包括：半导体衬底; 一组层间电介质层，从最靠近衬底的最下层的层间电介质层堆叠到距离衬底最远的最上层的层间电介质层，层间电介质层组中的每个层间电介质层包括导电线，电线的顶表面基本上 与对应的层间电介质层的顶表面共面; 接触最上面的层间电介质层的焊盘的导电的最终焊盘; 与所述端子焊盘的顶表面接触的导电电镀基层; 以及镀覆基底层上的铜块。

公开(公告)号：US20120009771A1

公开(公告)日：2012-01-12

申请号：US12833272

申请日：2010-07-09

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/3205

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。

公开(公告)号：US08008199B2

公开(公告)日：2011-08-30

申请号：US12869113

申请日：2010-08-26

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US20100323517A1

公开(公告)日：2010-12-23

申请号：US12869113

申请日：2010-08-26

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, JR. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, JR. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US07843063B2

公开(公告)日：2010-11-30

申请号：US12031103

申请日：2008-02-14

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, Jr. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。