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    Low density, high porosity material as gate dielectric for field emission device
    1.
    发明授权
    Low density, high porosity material as gate dielectric for field emission device 失效

    公开(公告)号：US5569058A

    公开(公告)日：1996-10-29

    申请号：US461230

    申请日：1995-06-05

    申请人： Bruce Gnade ,  Chih-Chen Cho ,  Jules D. Levine

    发明人： Bruce Gnade ,  Chih-Chen Cho ,  Jules D. Levine

    IPC分类号： H01J1/304 ,  H01J1/30 ,  H01J9/18

    CPC分类号： H01J1/3042 ,  H01J2201/319 ,  H01J2329/00

    摘要： A porous dielectric material such as silica-based aerogel is used as the dielectric layer 48 between the gate and the cathode on the emitter plate 12 of a field emission device. Aerogel, which can have a relative dielectric constant as low as 1.03, is deposited over the resistive layer 44 of the emitter plate 12. Metal layer 49, functioning as the gate electrode, is subsequently deposited over the aerogel layer 48. The use of aerogel as a gate dielectric reduces power consumption. In a disclosed embodiment, aerogel layer 48 is comprised of sublayers 48a, 48b, and 48c of aerogels of differing densities, thereby providing better adhesion of the aerogel gate dielectric to both the resistive layer 44 and metal layer 49. Methods of fabricating the aerogel gate dielectric are disclosed.

    Low density, high porosity material as gate dielectric for field emission device
    2.
    发明授权
    Low density, high porosity material as gate dielectric for field emission device 失效
    低密度，高孔隙率材料作为场致发射器件的栅极电介质

    公开(公告)号：US5525857A

    公开(公告)日：1996-06-11

    申请号：US292915

    申请日：1994-08-19

    申请人： Bruce Gnade ,  Chih-Chen Cho ,  Jules D. Levine

    发明人： Bruce Gnade ,  Chih-Chen Cho ,  Jules D. Levine

    IPC分类号： H01J1/304 ,  H01J1/30

    CPC分类号： H01J1/3042 ,  H01J2201/319 ,  H01J2329/00

    摘要： A porous dielectric material such as silica-based aerogel is used as the dielectric layer 48 between the gate and the cathode on the emitter plate 12 of a field emission device. Aerogel, which can have a relative dielectric constant as low as 1.03, is deposited over the resistive layer 44 of the emitter plate 12. Metal layer 49, functioning as the gate electrode, is subsequently deposited over the aerogel layer 48. The use of aerogel as a gate dielectric reduces power consumption. In a disclosed embodiment, aerogel layer 48 is comprised of sublayers 48a, 48b, and 48c of aerogels of differing densities, thereby providing better adhesion of the aerogel gate dielectric to both the resistive layer 44 and metal layer 49. Methods of fabricating the aerogel gate dielectric are disclosed.

    摘要翻译： 诸如二氧化硅基气凝胶之类的多孔电介质材料被用作场发射器件的发射极板12上的栅极和阴极之间的电介质层48。 可以具有低至1.03的相对介电常数的气凝胶沉积在发射极板12的电阻层44上。作为栅极的金属层49随后沉积在气凝胶层48上。使用气凝胶 作为栅极电介质降低功耗。 在公开的实施例中，气凝胶层48由不同密度的气凝胶的子层48a，48b和48c组成，从而提供气凝胶栅极电介质与电阻层44和金属层49两者的更好的附着。制造气凝胶门 电介质。

    OPERATING METHOD OF NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    OPERATING METHOD OF NON-VOLATILE MEMORY DEVICE 审中-公开
    非易失性存储器件的操作方法

    公开(公告)号：US20090021986A1

    公开(公告)日：2009-01-22

    申请号：US12236999

    申请日：2008-09-24

    申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

    发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

    IPC分类号： G11C11/34

    CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  Y10S438/954

    摘要： An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell.

    摘要翻译： 用于非易失性存储器件的操作方法适用于其中设置衬底的非易失性存储器件。 衬底包括沟槽，设置在衬底中的第一导电类型的第一阱区域和设置在第一导电类型的第一阱区域上方的第二导电类型的第二阱区域。 操作方法包括将第一电压施加到控制栅极，将第二电压施加到漏极区域，并将第三电压施加到源极区域。 此外，采用信道F-N隧道效应来对存储器单元进行编程。

    OPERATING METHOD OF A NON-VOLATILE MEMORY
    4.
    发明申请
    OPERATING METHOD OF A NON-VOLATILE MEMORY 审中-公开
    非易失性存储器的操作方法

    公开(公告)号：US20070263448A1

    公开(公告)日：2007-11-15

    申请号：US11778657

    申请日：2007-07-17

    申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

    发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

    摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

    摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

    NON-VOLATILE MEMORY CELL, FABRICATION METHOD AND OPERATING METHOD THEREOF
    6.
    发明申请
    NON-VOLATILE MEMORY CELL, FABRICATION METHOD AND OPERATING METHOD THEREOF 审中-公开
    非挥发性记忆体，制造方法及其操作方法

    公开(公告)号：US20060039200A1

    公开(公告)日：2006-02-23

    申请号：US10907031

    申请日：2005-03-17

    申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

    发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

    IPC分类号： G11C7/10

    CPC分类号： G11C16/0483 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11568

    摘要： A non-volatile memory including a plurality of memory units is provided. Each of the memory units includes a first memory cell and a second memory cell. The first memory cell is disposed over the substrate. The second memory cell is disposed next to the sidewall of the first memory cell and over the substrate. The first memory cell includes a first gate disposed over the substrate, a first composite dielectric layer disposed between the first gate and the substrate. The second memory cell includes a second gate disposed over the substrate and a second composite dielectric layer disposed between the second gate and the substrate and between the second gate and the first memory cell. Each of the first and second composite dielectric layers includes a bottom dielectric layer, a charge-trapping layer and a top dielectric layer.

    摘要翻译： 提供包括多个存储单元的非易失性存储器。 每个存储单元包括第一存储单元和第二存储单元。 第一存储单元设置在衬底上。 第二存储单元设置在第一存储单元的侧壁旁边且在衬底上。 第一存储单元包括设置在衬底上的第一栅极，设置在第一栅极和衬底之间的第一复合介电层。 第二存储单元包括设置在衬底上的第二栅极和设置在第二栅极和衬底之间以及第二栅极和第一存储单元之间的第二复合电介质层。 第一和第二复合电介质层中的每一个包括底部电介质层，电荷俘获层和顶部电介质层。

    Apparatus for increasing SRAM cell capacitance with metal fill
    7.
    发明申请
    Apparatus for increasing SRAM cell capacitance with metal fill 审中-公开
    用于通过金属填充增加SRAM单元电容的装置

    公开(公告)号：US20050151198A1

    公开(公告)日：2005-07-14

    申请号：US11057302

    申请日：2005-02-11

    申请人： Zhongze Wang ,  Chih-Chen Cho

    发明人： Zhongze Wang ,  Chih-Chen Cho

    IPC分类号： G11C11/412 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76

    CPC分类号： G11C11/4125 ,  G11C11/412 ,  H01L21/76885 ,  H01L27/11 ,  H01L27/1104

    摘要： A static random access memory cell with metal fill to form capacitors for increasing the capacitance of the memory cell. More specifically, a semiconductor device including a structure having an upper surface and a contact surface formed at the upper surface of the structure. A dielectric material is formed over the contact surface with a first conductive node and a second conductive node extending beyond the dielectric material. Dielectric spacers are formed around the first and second conductive nodes and conductive elements are formed between the dielectric spacers. The conductive elements and spacers form capacitors without implementing additional masking steps.

    摘要翻译： 具有金属填充的静态随机存取存储器单元以形成用于增加存储单元的电容的电容器。 更具体地说，一种半导体器件，包括具有形成在该结构的上表面上的上表面和接触表面的结构。 介电材料在接触表面上与第一导电节点和延伸超出电介质材料的第二导电节点形成。 电介质隔板围绕第一和第二导电节点形成，并且导电元件形成在电介质间隔件之间。 导电元件和间隔件形成电容器而不实施附加的掩蔽步骤。

    Backend metallization method and device obtained therefrom
    8.
    发明授权
    Backend metallization method and device obtained therefrom 失效
    后端金属化方法和由其获得的器件

    公开(公告)号：US06858937B2

    公开(公告)日：2005-02-22

    申请号：US09517314

    申请日：2000-03-02

    申请人： Chih-Chen Cho

    发明人： Chih-Chen Cho

    IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/58

    CPC分类号： H01L21/31116 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.

    摘要翻译： 对半导体器件及其制造方法进行说明。 在形成半导体器件期间，由耐蚀刻材料形成硬掩模。 掩模防止蚀刻剂蚀刻导电塞附近的电介质材料内的区域。 掩模可以由氮化物形成。 然后将导电材料沉积在蚀刻通孔内并与导电塞接触。

    Method of forming a field effect transistor
    9.
    发明授权
    Method of forming a field effect transistor 失效
    形成场效应晶体管的方法

    公开(公告)号：US06599789B1

    公开(公告)日：2003-07-29

    申请号：US09713844

    申请日：2000-11-15

    申请人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    发明人： Todd R. Abbott ,  Zhongze Wang ,  Jigish D. Trivedi ,  Chih-Chen Cho

    IPC分类号： H01L2184

    CPC分类号： H01L29/66651 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66636

    摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

    摘要翻译： 形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。 源极/漏极区域形成在沟道区域的相对侧上。 绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。 形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。 半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。 半导体通道材料形成在空隙内。 相邻的源极/漏极区域横向靠近通道材料提供。 在通道材料上形成一个栅极。 集成电路包括体半导体衬底。 其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。 在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。 场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。 考虑其他方面。