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    Endpoint detection system and method for plasma etching
    1.
    发明授权
    Endpoint detection system and method for plasma etching 失效
    端点检测系统和等离子体蚀刻方法

    公开(公告)号：US4954212A

    公开(公告)日：1990-09-04

    申请号：US412697

    申请日：1989-09-26

    申请人： Calvin T. Gabriel ,  James E. Nulty

    发明人： Calvin T. Gabriel ,  James E. Nulty

    IPC分类号： H01J37/32

    CPC分类号： H01J37/32935

    摘要： A plasma etching endpoint detection system and method for plasma etching systems generates an endpoint signal when the etching system completes the etching of a designated layer on a semiconductor wafer and begins etching the layer below the designated layer. An impedance transformation circuit is tuned so that the selected tuning point has a predefined relationship to the point at which minimum power reflection occurs. As a result, when the etching system completes the etching of a designated layer, the amount of power reflected by the plasma etcher will change in a predefined fashion so as to facilitate the generation of an endpoint signal. In one embodiment, a tuning capacitor in the etcher's impedance transformation circuit is set at a level at which it is known that the amount of reflected power will increase when the designated layer has been completely etched. As a result, the intensity of light generated in the plasma will decrease at the endpoint of etching the designated layer. An optical sensor, which is tuned to a frequency at which light is generated while the designated layer is being etched, generates an endpoint signal when the emission intensity decreases below a specified level, and that endpoint signal is used to turn off the etcher's plasma power supply. In another embodiment, the plasma etcher's controller detects when the reflected power increases above a specified level, at which point it generates an endpoint signal that is used to turn off the etcher's plasma power supply.

    摘要翻译： 当蚀刻系统完成半导体晶片上的指定层的蚀刻并开始蚀刻指定层下面的层时，用于等离子体蚀刻系统的等离子体蚀刻终点检测系统和方法产生端点信号。 调整阻抗变换电路，使得所选择的调谐点与发生最小功率反射的点具有预定的关系。 结果，当蚀刻系统完成对指定层的蚀刻时，由等离子体蚀刻器反射的功率量将以预定的方式改变，以便于产生端点信号。 在一个实施例中，蚀刻器阻抗变换电路中的调谐电容器被设置为已知当指定层已被完全蚀刻时反射功率的量将增加的水平。 结果，在蚀刻指定层的终点，等离子体中产生的光的强度将降低。 调光到指定层被蚀刻时产生光的频率的光学传感器当发射强度降低到低于指定水平时产生端点信号，并且该端点信号用于关闭蚀刻器的等离子体功率 供应。 在另一个实施例中，等离子体蚀刻器的控制器检测反射功率何时增加到高于指定水平，此时它产生用于关闭蚀刻器等离子体电源的端点信号。

    Method for forming a stable plasma
    2.
    发明授权
    Method for forming a stable plasma 失效
    形成稳定等离子体的方法

    公开(公告)号：US5441596A

    公开(公告)日：1995-08-15

    申请号：US281438

    申请日：1994-07-27

    申请人： James E. Nulty

    发明人： James E. Nulty

    IPC分类号： H01J37/32 ,  H05H1/46 ,  H05H1/00

    CPC分类号： H01J37/32082 ,  H05H1/46

    摘要： A method for forming a stable plasma, particularly in the high power and low pressure ranges. The method may be used in a plasma system such as that used for a plasma etch. First, the radio frequency power is turned on under low power and high pressure. The plasma is allowed to stabilize without tuning. Next, the pressure is dropped to the desired operating level and the tuning system is engaged. After tuning at the low power and low pressure, the radio frequency power is ramped to the desired level. Finally, the system is again tuned at the higher power.

    摘要翻译： 用于形成稳定等离子体的方法，特别是在高功率和低压范围内。 该方法可以用于诸如用于等离子体蚀刻的等离子体系统中。 首先，在低功率和高压下接通射频电源。 允许等离子体稳定而不调谐。 接下来，压力下降到期望的操作水平并且调谐系统被接合。 在低功耗和低压下调谐后，射频功率将上升到所需的水平。 最后，系统再次以较高的功率调谐。

    Method for etching and/or patterning a silicon-containing layer
    3.
    发明授权
    Method for etching and/or patterning a silicon-containing layer 有权
    蚀刻和/或图案化含硅层的方法

    公开(公告)号：US06890860B1

    公开(公告)日：2005-05-10

    申请号：US09345173

    申请日：1999-06-30

    申请人： Tinghao F. Wang ,  Usha Raghuram ,  James E. Nulty

    发明人： Tinghao F. Wang ,  Usha Raghuram ,  James E. Nulty

    IPC分类号： H01L21/302 ,  H01L21/3213 ,  H01L21/461

    CPC分类号： H01L21/32137 ,  H01L21/32139

    摘要： Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 Å of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2 or another etch having an etch rate of approximately 3000 Å/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

    摘要翻译： 在集成电路制造期间蚀刻多层II层之前，使用氢氟酸（HF）浸渍来从多晶硅层去除表面氧化物，并使用各向异性除氧操作来除去从 图案化操作。 在图案化之后，在多晶硅层被蚀刻之前，使用各向异性突破蚀刻剂（例如，基于碳氟化合物的蚀刻剂）进行长的穿透蚀刻（例如足以除去300-1500的氧化物）。 如果超过第一次浸渍和蚀刻之间的预定时间，HF浸渍可能会重复。 各向异性除氧操作可以使用各向异性抗反射涂层（ARC）蚀刻来进行，例如，Cl 2/2 O 2，HBr / O 2， 或者另一种蚀刻速率约为3000 / min的蚀刻约10-20秒。 多晶硅层可以在其蚀刻之后（但不是之前）退火。

    Method and apparatus for end point detection
    4.
    发明授权
    Method and apparatus for end point detection 失效
    终点检测方法及装置

    公开(公告)号：US5045149A

    公开(公告)日：1991-09-03

    申请号：US542811

    申请日：1990-06-22

    申请人： James E. Nulty

    发明人： James E. Nulty

    IPC分类号： G01N21/62 ,  H01J37/32

    CPC分类号： H01J37/32935 ,  G01N21/62

    摘要： A method and an apparatus for detecting the endpoint in a plasma etching process is disclosed. The invention uses a positive filter and a negative filter simultaneously to generate a first and a second signal respectively. The first and second signals are combined to form a combined signal. A change in the combined signal is indicative of the endpoint.

    摘要翻译： 公开了一种用于在等离子体蚀刻工艺中检测端点的方法和装置。 本发明同时使用正滤波器和负滤波器分别产生第一和第二信号。 第一和第二信号被组合以形成组合信号。 组合信号的变化表示端点。

    Method of fabricating a probe card
    6.
    发明授权
    Method of fabricating a probe card 有权
    制造探针卡的方法

    公开(公告)号：US07685705B2

    公开(公告)日：2010-03-30

    申请号：US12008483

    申请日：2008-01-11

    申请人： James E. Nulty ,  James A. Hunter ,  Alexander J. Herrera

    发明人： James E. Nulty ,  James A. Hunter ,  Alexander J. Herrera

    IPC分类号： H01R9/00 ,  H05K3/00

    CPC分类号： G01R1/07314 ,  G01R1/0735 ,  G01R1/07371 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49155

    摘要： A probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.

    摘要翻译： 用于在晶片上测试晶片的探针卡包括基底，在其表面上形成的多个悬臂和从悬臂的未支撑端延伸的多个探针。 悬臂的未支撑的端部突出在基板表面上的空腔上。 探针具有接触被测试骰子上的垫的提示。 探针卡可以包括在衬底的表面上方的压缩层，其具有探针延伸穿过的多个孔。

    Structure having reduced lateral spacer erosion
    8.
    发明授权
    Structure having reduced lateral spacer erosion 有权
    具有减少横向间隔物侵蚀的结构

    公开(公告)号：US06784552B2

    公开(公告)日：2004-08-31

    申请号：US09540610

    申请日：2000-03-31

    申请人： James E. Nulty ,  Christopher J. Petti

    发明人： James E. Nulty ,  Christopher J. Petti

    IPC分类号： H01L2348

    CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76838 ,  H01L21/823425 ,  H01L21/823475

    摘要： A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on a semiconductor body, then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate electrode. An etch stop layer is deposited adjacent the insulating layer, followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer, but retains the substantially rectangular lateral spacer profile of the first insulating layer. The apparatus is capable of maintaining high quality contacts between the conductive material in the contact region and an underlying device region such as a source or drain, or some other layer or structure, and is an effective structure for small feature size structures, particularly self-aligned contact structures.

    摘要翻译： 公开了一种使邻近接触区域的绝缘层的横向间隔物侵蚀最小化的方法以及相对于栅电极或其他结构提供具有小对准公差的接触开口的装置。 该方法包括以下步骤：在半导体本体上形成导电层，然后沉积与导电层相邻的绝缘层。 接下来，与栅电极相邻地形成大致矩形的绝缘间隔物。 在绝缘层附近沉积蚀刻停止层，随后进行蚀刻以从接触区域去除蚀刻停止层材料。 该蚀刻在其中蚀刻去除蚀刻停止层但保留第一绝缘层的基本上矩形的横向间隔物轮廓的条件下进行。 该装置能够在接触区域中的导电材料和诸如源极或漏极或其它一些层或结构的下面的器件区域之间保持高质量的接触，并且是小尺寸特征结构的有效结构， 对齐的接触结构。

    Advanced probe card and method of fabricating same
    9.
    发明授权
    Advanced probe card and method of fabricating same 有权
    先进的探针卡及其制造方法

    公开(公告)号：US07112975B1

    公开(公告)日：2006-09-26

    申请号：US10784566

    申请日：2004-02-23

    申请人： Bo Jin ,  James E. Nulty

    发明人： Bo Jin ,  James E. Nulty

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2889 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of holes may extend through the SOI layer and the plurality of probe dice, with each hole corresponding to a pad on a probe die. The anti-wafer structure may be advantageously used in an advanced probe card. Techniques for fabricating an anti-wafer and an advanced probe card are also disclosed.

    摘要翻译： 在一个实施例中，抗晶片结构包括绝缘体上硅（SOI）层和形成在SOI层上的多个探针骰子。 每个探针管芯可以具有对应于待测晶片上的管芯的焊盘布局的焊盘布局。 多个孔可以延伸通过SOI层和多个探针骰子，每个孔对应于探针管芯上的焊盘。 反晶片结构可以有利地用于高级探针卡中。 还公开了用于制造抗晶片和高级探针卡的技术。