公开(公告)号：US08130881B1

公开(公告)日：2012-03-06

申请号：US12244401

申请日：2008-10-02

申请人： Carroll Philip Gossett ,  Michial Allen Gunter ,  Paul K. Rodman

发明人： Carroll Philip Gossett ,  Michial Allen Gunter ,  Paul K. Rodman

IPC分类号： H04B1/10

CPC分类号： H04B7/0848 ,  H04L25/03038 ,  H04L2025/03375 ,  H04L2025/03426 ,  H04L2025/03458 ,  H04L2025/03477

摘要： Systems, methods, and devices for MIMO communications with reduced compute complexity are disclosed. Spectrally whitened communications are received, magnitude distortion is removed and phase distortion is corrected. The magnitude distortion is removed separately from the correction of the phase distortion, thereby reducing the compute complexity.

摘要翻译： 公开了具有降低的计算复杂度的用于MIMO通信的系统，方法和设备。 接收到光谱白化通信，去除幅度失真并校正相位失真。 与相位失真的校正分开去除幅度失真，从而降低计算复杂度。

公开(公告)号：US4761755A

公开(公告)日：1988-08-02

申请号：US629640

申请日：1984-07-11

申请人： Joseph L. Ardini, Jr. ,  Robert F. Beckwith ,  Chi-Ping Chen ,  Paul K. Rodman

发明人： Joseph L. Ardini, Jr. ,  Robert F. Beckwith ,  Chi-Ping Chen ,  Paul K. Rodman

IPC分类号： G06F7/575 ,  G06F7/76 ,  G06F9/22 ,  G06F7/38

CPC分类号： G06F7/76 ,  G06F7/575 ,  G06F9/226 ,  G06F2207/3856

摘要： A data processing system, wherein the central processing unit has an arithmetic element for processing data in response to machine program instructions and a control store for microcode program storage responsive to the machine instructions for implementing the instruction, has an improved arithmetic unit for enabling higher throughput without substantially increasing hardware cost. The arithmetic unit has a reconfigurable arithmetic logic unit which is controlled in response to both hardware generated data signals and microcode generated data signals. A data string manipulation circuitry provides for aligning data strings for processing by the arithmetic logic unit. Circuitry is provided, responsive to a decoded machine instruction, for generating control signals for configuring the arithmetic unit and for controlling the data string manipulation circuitry. As a result, the number of microcode steps needed to implement particular decimal and string manipulation machine instructions is significantly reduced, thereby saving machine cycles, while the additional hardware cost is very modest.

摘要翻译： 一种数据处理系统，其中中央处理单元具有用于响应于机器程序指令处理数据的算术元件和响应于用于实现该指令的机器指令的微代码程序存储的控制存储器，具有改进的运算单元，用于实现更高的吞吐量 而不会显着增加硬件成本。 算术单元具有可重配置的算术逻辑单元，该单元响应于硬件产生的数据信号和微码产生的数据信号而被控制。 数据串操作电路提供对准数据串以供运算逻辑单元处理。 提供响应于解码的机器指令的电路，用于产生用于配置运算单元和用于控制数据串操纵电路的控制信号。 因此，实现特定十进制和字符串操纵机器指令所需的微代码步骤数量显着减少，从而节省机器周期，而额外的硬件成本非常适中。

公开(公告)号：US5307506A

公开(公告)日：1994-04-26

申请号：US945571

申请日：1992-09-16

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F13/40

CPC分类号： G06F13/4022

摘要： A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the cluster having at least one integer processor and one floating point processor. A plurality of I/F buses interconnect the integer and floating point processors of a cluster for communications therebetween. Integer load buses connect the integer processors of each cluster and selectively connect those processors to the memory controllers for transferring data from memory to the clusters and for providing inter-integer processor data communications. A plurality of floating point load buses connect the floating point processors of the clusters to selected memory controllers for transferring data from the controllers to the floating point processors and for providing inter-floating point processor data communications. A plurality of physical address buses provide one-way communications for transferring memory addresses from the integer processors to the memories and a plurality of storage buses connect the floating point processors to the memory controllers along a one-way communications path for transferring data to be stored in the memories. The hardware architecture provides advantageous communications between the elements of the data processing system for enabling wide bandwidth communications and high instruction throughput.

摘要翻译： 并行处理器具有多个通信总线，其有利地将算术处理器元件，存储器控制器元件，全局控制器电路和输入/输出处理器互连。 处理器优选地具有至少一个中央处理单元簇，该簇具有至少一个整数处理器和一个浮点处理器。 多个I / F总线互连簇的整数和浮点处理器，用于在其间进行通信。 整数负载总线连接每个集群的整数处理器，并将这些处理器选择性地连接到存储器控制器，以将数据从存储器传输到集群，并提供整数处理器数据通信。 多个浮点负载总线将集群的浮点处理器连接到选择的存储器控​​制器，用于将数据从控制器传送到浮点处理器，并提供浮点间处理器数据通信。 多个物理地址总线提供用于将存储器地址从整数处理器传送到存储器的单向通信，并且多个存储总线沿着单向通信路径将浮点处理器连接到存储器控制器，用于传送要存储的数据 在回忆中 硬件架构提供数据处理系统的元件之间的有利通信，以实现宽带宽通信和高指令吞吐量。

公开(公告)号：US5057837A

公开(公告)日：1991-10-15

申请号：US476108

申请日：1990-01-30

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/30149 ,  G06F12/0844 ,  G06F12/0875 ,  G06F9/30025 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3891

摘要： A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

摘要翻译： 一种用于将压缩形式的指令字存储在存储介质上的方法和装置，所述指令字具有多个指令字段，与每个指令字相关联的特征，具有至少等于 指令字中的指令字段。 每个指令字段与掩码字的位相关联，因此使用掩码字，只有非零指令字段需要存储在存储器中。 指令压缩方法有利地用在高速缓存未命中引擎中，用于在发生高速缓存未命中之后重新填充指令高速缓存的部分。

公开(公告)号：US5757658A

公开(公告)日：1998-05-26

申请号：US611785

申请日：1996-03-06

申请人： Paul K. Rodman ,  Marjorie S. Levine

发明人： Paul K. Rodman ,  Marjorie S. Levine

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A system and procedure for placement optimization of input/output ports associated with edges of circuit blocks within an integrated circuit design. The integrated circuit design is composed of circuit blocks that communicate using inter-block signal wires coupled to input/output ports (IOPs) located along edges of circuit blocks. An arbitrary IOP placement is first received, e.g., from a global floorplanner, and indicates (1) the allowable edge placement domains for each IOP and can optionally include (2) an arbitrary IOP placement within these allowable edge domains. A cell placer (e.g., a quadratic based standard cell placer) receives the arbitrary IOP placement and, for each circuit block, places cells represented within internal netlists. The placer does not optimize the placement of the IOPs. For each IOP, the set of cells of the net that is coupled to the IOP is determined. Each IOP is then moved, within its allowable edge placement, to a position closest to the nearest cell that is within its associated net. The above sequence is then repeated a number of times (e.g., IOPs are moved and the placer is run again); upon each run the routability of the placement is estimated. After the above iterations, the present invention accepts the placement with the best estimated routability and this placement is then routed by a router. By taking into account the position of cells associated with an IOP, and displacing the IOP near these cells, the internal circuit is more efficiently placed which reduces the size of the circuit block up to 30 percent.

摘要翻译： 用于在集成电路设计中与电路块的边缘相关联的输入/输出端口的放置优化的系统和过程。 集成电路设计由电路块组成，电路块使用耦合到位于电路块边缘的输入/输出端口（IOP）的块间信号线进行通信。 首先接收任意的IOP放置，例如来自全球平板电脑，并且指示（1）每个IOP的可允许的边缘放置域，并且可以可选地包括（2）在这些可允许边缘域内的任意IOP放置。 单元放置器（例如，基于二次的标准单元放置器）接收任意的IOP放置，并且对于每个电路块，放置在内部网表中表示的单元。 放置器不能优化IOP的放置。 对于每个IOP，确定耦合到IOP的网络的单元组。 然后将每个IOP在其允许的边缘放置内移动到最靠近其相关网内的最近细胞的位置。 然后重复上述顺序多次（例如，移动IOP并再次运行放置器）; 在每次运行时，估计布局的可布线性。 在上述迭代之后，本发明接受具有最佳估计可路由性的布置，并且该布置然后被路由器路由。 通过考虑到与IOP相关联的单元的位置，并且移位这些单元附近的IOP，内部电路被更有效地放置，这将电路块的尺寸减小到30％。

公开(公告)号：US5179680A

公开(公告)日：1993-01-12

申请号：US707917

申请日：1991-05-30

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3891 ,  G06F12/0844 ,  G06F12/0875 ,  G06F9/30025 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/321 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885

摘要： A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

摘要翻译： 一种用于将压缩形式的指令字存储在存储介质上的方法和装置，所述指令字具有多个指令字段，与每个指令字相关联的特征，具有至少等于 指令字中的指令字段。 每个指令字段与掩码字的位相关联，因此使用掩码字，只有非零指令字段需要存储在存储器中。 指令压缩方法有利地用在高速缓存未命中引擎中，用于在发生高速缓存未命中之后重新填充指令高速缓存的部分。

公开(公告)号：US4747043A

公开(公告)日：1988-05-24

申请号：US32990

申请日：1987-03-27

申请人： Paul K. Rodman

发明人： Paul K. Rodman

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0831 ,  G06F12/0817

摘要： A cache coherence system for a multiprocessor system including a plurality of data processors coupled to a common main memory. Each of the data processors includes an associated cache memory having storage locations therein corresponding to storage locations in the main memory. The cache coherence system for a data processor includes a cache invalidate table (CIT) memory having internal storage locations corresponding to locations in the cache memory of the data processor. The cache coherence system detects when the contents of storage locations in the cache memories of the one or more of the data processors have been modified in conjuction with the activity those data processors and is responsive to such detections to generate and store in its CIT memory a multiple element linked list defining the locations in the cache memories of the data processors having modified contents. Each element of the list defines one of those cache storage locations and also identifies the location in the CIT memory of the next element in the list.

摘要翻译： 一种用于多处理器系统的高速缓存一致性系统，包括耦合到公共主存储器的多个数据处理器。 每个数据处理器包括相关联的高速缓冲存储器，其中存储位置对应于主存储器中的存储位置。 用于数据处理器的高速缓存一致性系统包括具有对应于数据处理器的高速缓冲存储器中的位置的内部存储位置的高速缓存无效表（CIT）存储器。 高速缓存一致性系统检测一个或多个数据处理器的高速缓冲存储器中的存储位置的内容何时已被修改，并且响应于这些检测来生成和存储在其CIT存储器中的这些数据处理器的活动 多元素链接列表定义具有修改内容的数据处理器的高速缓冲存储器中的位置。 列表的每个元素定义了这些缓存存储位置之一，并且还标识了列表中下一个元素的CIT存储器中的位置。

公开(公告)号：US4920477A

公开(公告)日：1990-04-24

申请号：US40990

申请日：1987-04-20

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F11/14 ,  G06F12/10

CPC分类号： G06F12/1063 ,  G06F11/1407

摘要： A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.

摘要翻译： 数据处理器具有中央处理单元和至少一个流水线存储器控制器电路。 中央处理单元使用虚拟地址存储器表后置缓冲器来对存储器中的数据进行寻址，并具有数据未命中恢复电路，其中在检测到存储器访问错误状况之后，引起错误状态的指令，以及进入存储器管线的指令 导致错误状态的指令后，重播。 用于重放指令的方法和装置使用先进先出的缓冲器来存储与每个存储器访问指令相关的虚拟地址数据和指令状态数据。 然后在检测到错误条件之后检索存储的数据，使得可以重放从数据未命中开始的指令序列。

公开(公告)号：US4833599A

公开(公告)日：1989-05-23

申请号：US41081

申请日：1987-04-20

申请人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

发明人： Robert P. Colwell ,  John O'Donnell ,  David B. Papworth ,  Paul K. Rodman

IPC分类号： G06F9/26 ,  G06F9/28 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30094 ,  G06F9/264 ,  G06F9/28 ,  G06F9/30061 ,  G06F9/3842 ,  G06F9/3885

摘要： In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

摘要翻译： 在具有多个单独操作的算术处理单元的并行数据处理系统中，一种方法和装置允许在单个机器周期中操作多个分支指令。 分支指令已经与分层优先级系统相关联，并且该方法和装置确定应该采用哪个分支（如果有的话）。 特别地，该方法和装置在并行执行分支指令期间同时确定与分支指令相关联的任何分支测试条件是否为真，并且独立地确定每个分支指令的目标地址和下降指令地址if 不执行分支指令。

公开(公告)号：US4750154A

公开(公告)日：1988-06-07

申请号：US629349

申请日：1984-07-10

申请人： Brian Lefsky ,  Paul K. Rodman ,  Stephen S. Corbin

发明人： Brian Lefsky ,  Paul K. Rodman ,  Stephen S. Corbin

IPC分类号： G06F5/06 ,  G06F9/312 ,  G06F9/38 ,  G06F13/16 ,  G06F13/42 ,  G11C5/00

CPC分类号： G06F9/30043 ,  G06F13/1631 ,  G06F13/4234 ,  G06F5/065 ,  G06F9/3824 ,  G06F9/3826

摘要： A memory alignment system and method are disclosed having a memory bus designed to accommodate more than one write instruction at a time and where data from different write instructions are merged together when the writes are destined for alignable locations in memory. In one embodiment, a write buffer and a comparator are configured to compare successive instructions for alignable destination addresses. In another embodiment, a content associative buffer is employed to compare the address of a write instruction with the addresses of all other stored write instructions. A variable scheduler to control the unloading of the buffer is also disclosed as is an apparatus for merging data read from memory with data awaiting transmission to memory to obtain the most up-to-date version.

摘要翻译： 公开了一种存储器对准系统和方法，其具有设计成一次容纳多于一个写指令的存储器总线，并且当写入目的地是存储器中可对准位置时，来自不同写指令的数据被合并在一起。 在一个实施例中，写缓冲器和比较器被配置为比较可对准目的地地址的连续指令。 在另一个实施例中，使用内容关联缓冲器来将写指令的地址与所有其它存储的写指令的地址进行比较。 还公开了一种用于控制缓冲器卸载的可变调度器，用于将从存储器读取的数据与等待传输到存储器的数据合并以获得最新版本的装置。