公开(公告)号：US06650008B2

公开(公告)日：2003-11-18

申请号：US10105155

申请日：2002-03-26

申请人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC分类号： H01L2302

CPC分类号： H01L23/3128 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stacked semiconductor packaging device consists of at least a stacked multi-chip device comprising a substrate. A first chip has a back surface faced towards the substrate and an active surface comprising a plurality of bonding pads which have a first set of elongate conductors connected to the substrate. A second chip has another back surface and another active surface comprising a plurality of bonding pads which have a second set of elongate conductors connected to the substrate. The active surface of the second chip is faced towards the active surface of said first chip and is stacked atop the first chip so as to expose all of the bonding pads. The face-to-face arrangement of the first chip and the second chip can reduce the whole packing height.

摘要翻译： 层叠的半导体封装装置至少由包括衬底的堆叠式多芯片器件构成。 第一芯片具有面向衬底的后表面，并且活性表面包括多个接合焊盘，其具有连接到衬底的第一组细长导体。 第二芯片具有另一个背面，另一个活性表面包括多个键合焊盘，其具有连接到衬底的第二组细长导体。 第二芯片的有源表面面向所述第一芯片的有源表面，并且堆叠在第一芯片的顶部，以暴露所有焊盘。 第一芯片和第二芯片的面对面布置可以降低整个包装高度。

公开(公告)号：US07122904B2

公开(公告)日：2006-10-17

申请号：US10131485

申请日：2002-04-25

申请人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

摘要： A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

公开(公告)号：US06977436B2

公开(公告)日：2005-12-20

申请号：US10074052

申请日：2002-02-14

申请人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC分类号： H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

CPC分类号： H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532

摘要： A semiconductor packaging device has a carrier having at least a portion configured for containing a chip. The chip, affixing to the portion with sidewall, has a back surface an active surface, which multitudes of bonding pads are on the active surface. One insulating layer on the active surface and carrier has multitudes of conductive holes corresponding to the first bonding pads. A multi-layer structure on the insulating layer is configured for providing electrical connection to the conductive holes. Another insulating layer, affixed on one of the carrier and the multi-layer structure, has another conductive holes electrically connected to the conductive holes. Multitudes of solder balls, on at least one of the carrier and latter insulating layer, electrically connect the latter conductive holes.

摘要翻译： 半导体封装装置具有至少一部分被配置为容纳芯片的载体。 固定在具有侧壁的部分上的芯片具有背表面，其中多个接合焊盘位于活性表面上。 有源表面和载体上的一个绝缘层具有对应于第一接合焊盘的多个导电孔。 绝缘层上的多层结构构造成用于提供与导电孔的电连接。 固定在载体和多层结构之一上的另一绝缘层具有电连接到导电孔的另一导电孔。 在载体和后一绝缘层中的至少一个上的大量焊球电连接后面的导电孔。

公开(公告)号：US06559526B2

公开(公告)日：2003-05-06

申请号：US09842133

申请日：2001-04-26

申请人： Jui-Chung Lee ,  Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Jui-Chung Lee ,  Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23495

CPC分类号： H01L23/49575 ,  H01L23/49513 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2224/45015 ,  H01L2924/207

摘要： A structure of a stacked-type multi-chip stack package of the leadframe, the shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

摘要翻译： 可以调节引线框的堆叠式多芯片堆叠封装的结构，对于堆叠芯片的高和量来调节阶梯式内部引线的形状，并且可以匹配不同的焊接技术。 用于形成本结构的方法可以通过可见的设备和材料容易地进行，并且本结构可以提高接合过程的可靠性。 本发明可以堆叠多芯片（多于两个）。

公开(公告)号：US06972372B1

公开(公告)日：2005-12-06

申请号：US10856452

申请日：2004-05-28

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H05K5/06

CPC分类号： H01L23/49551 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacking structure is described that permits stacking of electrical components with no requirement for an ancillary stacking framework. Electrical components are fabricated with inner and outer lead portions that provide connection to a substrate and to other electrical components in a stack.

摘要翻译： 描述了堆叠结构，其允许电气部件的堆叠，而不需要辅助堆叠框架。 制造电气部件的内部和外部引线部分提供与基板和堆叠中的其他电气部件的连接。

公开(公告)号：US20050263311A1

公开(公告)日：2005-12-01

申请号：US10856452

申请日：2004-05-28

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H05K5/06

CPC分类号： H01L23/49551 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacking structure is described that permits stacking of electrical components with no requirement for an ancillary stacking framework. Electrical components are fabricated with inner and outer lead portions that provide connection to a substrate and to other electrical components in a stack.

摘要翻译： 描述了堆叠结构，其允许电气部件的堆叠，而不需要辅助堆叠框架。 制造电气部件的内部和外部引线部分提供与基板和堆叠中的其他电气部件的连接。

公开(公告)号：US07291927B2

公开(公告)日：2007-11-06

申请号：US10726577

申请日：2003-12-04

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dual chips stacked packaging structure. A first chip comprises an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads. A lead frame comprises a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, with the first adhering surface adhering to the active surface of the first chip in such a way as to avoid contact with the first bonding pads. A second chip comprises an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, and the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads. Parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.

摘要翻译： 双芯片堆叠包装结构。 第一芯片包括有源表面和相对的非活性表面，活性表面由具有多个第一键合焊盘的中心区域和外围区域组成。 引线框架包括多个引线和具有第一粘附表面和第二粘附表面的芯片焊盘，其中第一粘附表面粘附到第一芯片的有效表面以避免与第一焊盘接触 。 第二芯片包括与芯片焊盘的第二粘附表面连接的有源表面和相对的非有效表面，以及由具有多个第二焊盘的中心区域和外围区域组成的活性表面。 导线的一部分与第一焊盘和引线电连接，并且导线的一部分与第二焊盘和引线电连接。

公开(公告)号：US20050012184A1

公开(公告)日：2005-01-20

申请号：US10755469

申请日：2004-01-13

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/31 ,  H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor packaging structure. The structure comprises a chip, a lead frame, and a plurality of wires. The chip comprises an active surface and an opposing non-active surface, the active surface comprising a central area and a peripheral area having a plurality of bonding pads. The lead frame comprises a plurality of the leads, a plurality of tie bars, and a chip paddle. The tie bars is connected with the chip paddle and attached to the active surface of the chip in such a way as to avoid contact with the bonding pads. As well, the wires electrically connect with the bonding pad and the leads.

摘要翻译： 半导体封装结构。 该结构包括芯片，引线框架和多根导线。 芯片包括有源表面和相对的非有效表面，该有源表面包括具有多个焊盘的中心区域和周边区域。 引线框架包括多个引线，多个连接条和芯片桨。 连接杆与芯片桨连接，并且以避免与接合垫接触的方式附接到芯片的有源表面。 同样，电线与焊盘和引线电连接。

公开(公告)号：US20070052079A1

公开(公告)日：2007-03-08

申请号：US11219815

申请日：2005-09-07

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A multi-chip stacked package structure, including a leadframe base thin package structure with two or more chips in the stacking structure, is provided that is capable of including two or more stacked chips that reduce the total stacking thickness. The package structure also reduces stacking thickness by achieving stacking of four or more chips into the area of a thin small outline package structure.

摘要翻译： 提供了一种多芯片堆叠封装结构，其包括具有堆叠结构中的两个或更多个芯片的引线框底部薄封装结构，其能够包括减少总层叠厚度的两个或更多个堆叠芯片。 封装结构还通过实现将四个或更多个芯片堆叠到薄的小外形封装结构的区域中来减少堆叠厚度。

公开(公告)号：US20050001328A1

公开(公告)日：2005-01-06

申请号：US10726577

申请日：2003-12-04

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dual chips stacked packaging structure. A first chip comprises an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads. A lead frame comprises a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, with the first adhering surface adhering to the active surface of the first chip in such a way as to avoid contact with the first bonding pads. A second chip comprises an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, and the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads. Parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.

摘要翻译： 双芯片堆叠包装结构。 第一芯片包括有源表面和相对的非活性表面，活性表面由具有多个第一键合焊盘的中心区域和外围区域组成。 引线框架包括多个引线和具有第一粘附表面和第二粘附表面的芯片焊盘，其中第一粘附表面粘附到第一芯片的有效表面以避免与第一焊盘接触 。 第二芯片包括与芯片焊盘的第二粘附表面连接的有源表面和相对的非有效表面，以及由具有多个第二焊盘的中心区域和外围区域组成的活性表面。 导线的一部分与第一焊盘和引线电连接，并且导线的一部分与第二焊盘和引线电连接。