公开(公告)号：US08710681B2

公开(公告)日：2014-04-29

申请号：US13485527

申请日：2012-05-31

申请人： Chih-Horng Chang ,  Tin-Hao Kuo ,  Tsung-Fu Tsai ,  Min-Feng Ku

发明人： Chih-Horng Chang ,  Tin-Hao Kuo ,  Tsung-Fu Tsai ,  Min-Feng Ku

IPC分类号： H01L33/62 ,  H01L33/52 ,  H01L23/48

CPC分类号： H01L23/3121 ,  H01L21/304 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00

摘要： A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

摘要翻译： 一种装置包括第一包装部件和第二包装部件，所述第一包装部件和第二包装部件下面并结合到第一包装部件。 成型材料设置在第一包装部件下方并被模制到第一和第二包装部件上，其中成型材料和第一包装部件形成界面。 隔离区域包括第一边缘，其中隔离区域的第一边缘接触第一封装部件的第一边缘和模制材料的第一边缘。 隔离层的底部低于界面。

公开(公告)号：US20130320572A1

公开(公告)日：2013-12-05

申请号：US13485527

申请日：2012-05-31

申请人： Chih-Horng Chang ,  Tin-Hao Kuo ,  Tsung-Fu Tsai ,  Min-Feng Ku

发明人： Chih-Horng Chang ,  Tin-Hao Kuo ,  Tsung-Fu Tsai ,  Min-Feng Ku

IPC分类号： H01L23/28 ,  H01L21/56

CPC分类号： H01L23/3121 ,  H01L21/304 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00

摘要： A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

公开(公告)号：US08581399B2

公开(公告)日：2013-11-12

申请号：US13192826

申请日：2011-07-28

申请人： Tsung-Fu Tsai ,  Min-Feng Ku ,  Yian-Liang Kuo

发明人： Tsung-Fu Tsai ,  Min-Feng Ku ,  Yian-Liang Kuo

IPC分类号： H01L23/485

CPC分类号： H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03 ,  H01L2224/0345 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05005 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13027 ,  H01L2224/13147 ,  H01L2224/14132 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01078 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/0104 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device comprises a substrate comprising a major surface and a plurality of metal bumps on the major surface. Each of the plurality of metal bumps comprises a metal via on the major surface and a metal pillar on the metal via having an overlay offset between the metal pillar and metal via. A first metal bump of the metal bumps has a first overlay offset and a second metal bump of the metal bumps farther than the first metal bump to a centroid of the substrate has a second overlay offset greater than the first overlay offset.

摘要翻译： 半导体器件包括在主表面上包括主表面和多个金属凸块的衬底。 多个金属凸块中的每一个包括在主表面上的金属通孔和金属通孔上的金属柱，在金属柱和金属通孔之间具有覆盖偏移。 金属凸块的第一金属凸块具有第一覆盖偏移，并且比第一金属凸块更远的金属凸块的第二金属凸块与基板的质心具有大于第一叠加偏移的第二叠加偏移。