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    Semiconductor device design system and method of using the same
    1.
    发明授权
    Semiconductor device design system and method of using the same 有权
    半导体器件设计系统及其使用方法

    公开(公告)号：US08762897B2

    公开(公告)日：2014-06-24

    申请号：US13475853

    申请日：2012-05-18

    申请人： Chih-Hsien Chang ,  Yung-Chow Peng ,  Fu-Lung Hsueh

    发明人： Chih-Hsien Chang ,  Yung-Chow Peng ,  Fu-Lung Hsueh

    IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00 ,  G06F19/00

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F19/00 ,  G06F2217/12 ,  G21K5/00

    摘要： A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.

    摘要翻译： 电路设计系统包括被配置为产生电路的示意图信息和预着色信息的示意性设计工具。 电路设计系统还包括被配置为在非暂时计算机可读介质上存储原理图信息和预着色信息的网表文件，以及被配置为从网表文件中提取预着色信息的提取工具。 包括在电路设计系统中的布局设计工具被配置为基于原理图信息和预着色信息设计至少一个掩模。 电路设计系统还包括布局与示意性比较工具，其被配置为将至少一个掩模与示意图信息和预着色信息进行比较。

    Over stress verify design rule check
    2.
    发明授权
    Over stress verify design rule check 有权
    过压力验证设计规则检查

    公开(公告)号：US08510701B2

    公开(公告)日：2013-08-13

    申请号：US13350894

    申请日：2012-01-16

    申请人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

    发明人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.

    摘要翻译： 本公开的一些方面提供了电子设计自动化（EDA）技术，其在设计期间检查诸如晶体管或其他半导体器件的各个块是否连接到其正确的电源域。 以这种方式，所公开的EDA技术可以限制或防止在制造时应用于块的过应力条件并有助于提高集成电路的可靠性。

    Multi-phase clock generator and data transmission lines
    3.
    发明授权
    Multi-phase clock generator and data transmission lines 有权
    多相时钟发生器和数据传输线

    公开(公告)号：US08482332B2

    公开(公告)日：2013-07-09

    申请号：US13089160

    申请日：2011-04-18

    申请人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03K3/00

    CPC分类号： H03K5/15066 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/06

    摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

    摘要翻译： 实施例是集成电路。 集成电路包括时钟发生器和数据传输线。 时钟发生器产生时钟信号。 至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。 至少部分地通过至少一个时钟信号来触发每个数据传输线。

    High speed communication interface with an adaptive swing driver to reduce power consumption
    4.
    发明授权
    High speed communication interface with an adaptive swing driver to reduce power consumption 有权

    公开(公告)号：US08410818B1

    公开(公告)日：2013-04-02

    申请号：US13372978

    申请日：2012-02-14

    申请人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03K19/094

    CPC分类号： H03K3/012 ,  H03K19/0013 ,  H03K19/018521

    摘要： A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

    Multi-Phase Clock Generator and Data Transmission Lines
    5.
    发明申请
    Multi-Phase Clock Generator and Data Transmission Lines 有权
    多相时钟发生器和数据传输线

    公开(公告)号：US20120262209A1

    公开(公告)日：2012-10-18

    申请号：US13089160

    申请日：2011-04-18

    申请人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03L7/06 ,  H03L7/00

    CPC分类号： H03K5/15066 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/06

    摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.

    摘要翻译： 实施例是集成电路。 集成电路包括时钟发生器和数据传输线。 时钟发生器产生时钟信号。 至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。 至少部分地通过至少一个时钟信号来触发每个数据传输线。

    OVER STRESS VERIFY DESIGN RULE CHECK
    6.
    发明申请
    OVER STRESS VERIFY DESIGN RULE CHECK 有权
    超过应变验证设计规则检查

    公开(公告)号：US20130185688A1

    公开(公告)日：2013-07-18

    申请号：US13350894

    申请日：2012-01-16

    申请人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

    发明人： Chen-Ting Ko ,  Chih-Hsien Chang ,  Yung-Chow Peng

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.

    摘要翻译： 本公开的一些方面提供了电子设计自动化（EDA）技术，其在设计期间检查诸如晶体管或其他半导体器件的各个块是否连接到其正确的电源域。 以这种方式，所公开的EDA技术可以限制或防止在制造时应用于块的过应力条件并有助于提高集成电路的可靠性。

    Automated test apparatus for testing risk and integrity of pharmaceutical filtration membranes and method thereof
    9.
    发明申请
    Automated test apparatus for testing risk and integrity of pharmaceutical filtration membranes and method thereof 有权
    用于测试药物过滤膜的风险和完整性的自动化试验装置及其方法

    公开(公告)号：US20150033828A1

    公开(公告)日：2015-02-05

    申请号：US13956375

    申请日：2013-08-01

    申请人： Ming-Hsin Li ,  Shu-Pei Chiu ,  Chih-Hsien Chang ,  Te-Wei Lee

    发明人： Ming-Hsin Li ,  Shu-Pei Chiu ,  Chih-Hsien Chang ,  Te-Wei Lee

    IPC分类号： G01N15/08

    CPC分类号： B01D65/102 ,  B01D65/10 ,  G01M3/06

    摘要： An automated test apparatus for risk and integrity testing for pharmaceutical filtration membranes, including at least the following components: a liquid injection inlet, a pump, a fluid pressure gauge, a gas pressure gauge, a plurality of solenoid valves, a plurality of membranes, a gas pressure regulator valve, a pharmaceutical product bottle, and a bubble generation bottle. The automated test apparatus of the present invention is controlled by computer software in connection with an automatic pharmaceutical synthesis apparatus for automated testing. In use of the automated test apparatus of the present invention, it needs only to start the operating system of the automated test apparatus for membrane risk and integrity test after the completion of the automatic pharmaceutical synthesis. The membrane risk and integrity test can be accomplished in a short time by measuring pressures of gas and liquid with pressure gauges deposed online concurrently.

    摘要翻译： 一种用于药物过滤膜的风险和完整性测试的自动测试装置，包括至少以下组件：液体注射入口，泵，流体压力计，气体压力计，多个电磁阀，多个膜， 气体压力调节阀，药品瓶和气泡生成瓶。 本发明的自动测试装置由计算机软件与用于自动化测试的自动药物合成装置有关。 在使用本发明的自动测试装置时，仅需要在自动药物合成完成之后启动用于膜风险和完整性测试的自动测试装置的操作系统。 薄膜风险和完整性测试可以在短时间内通过测量气体和液体的压力同时在线排出的压力计来完成。

    Skew sensitive calculation for misalignment from multi patterning
    10.
    发明授权
    Skew sensitive calculation for misalignment from multi patterning 有权
    对多图案化的偏移的偏移计算

    公开(公告)号：US08589831B1

    公开(公告)日：2013-11-19

    申请号：US13561189

    申请日：2012-07-30

    申请人： Chih-Hsien Chang ,  Min-Shueh Yuan ,  Tsung-Hsien Tsai

    发明人： Chih-Hsien Chang ,  Min-Shueh Yuan ,  Tsung-Hsien Tsai

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Some aspects of the present disclosure provide for a method of accurately simulating variations in an operating parameter, due to processing variations caused by a multi-patterning exposure, by reducing the impact of layout sections having a large width and spacing. The method assigns a skew sensitive index to one or more sections of a multi-patterning layer formed with a first mask. Runlengths of the one or more sections are respectively multiplied by an assigned skew sensitive index to determine a skew variation for each of the one or more sections. The overall skew variation sum is then determined by summing the skew variation for each of the one or more sections. By separately determining the effects of processing variations (e.g., mask misalignment) for different sections of a multi-patterning layer, an accurate measurement of operating parameter variations is achieved.

    摘要翻译： 本公开的一些方面提供了通过减小​​具有大的宽度和间隔的布局部分的影响，由于由多图案化曝光引起的处理变化，准确地模拟操作参数的变化的方法。 该方法为由形成有第一掩模的多图案化层的一个或多个部分分配偏斜敏感指数。 一个或多个部分的运行长度分别乘以一个分配的偏移敏感指数，以确定一个或多个部分中的每个部分的偏斜变化。 然后通过对一个或多个部分中的每一个的偏斜变化求和来确定总体偏差变化和。 通过分别确定多图案化层的不同部分的处理变化（例如，掩模未对准）的影响，实现了操作参数变化的精确测量。