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    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area
    1.
    发明授权
    DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
    DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积

    公开(公告)号：US07161204B2

    公开(公告)日：2007-01-09

    申请号：US11098112

    申请日：2005-04-04

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Fu-Liang Yang ,  Chia-Hui Lin ,  Chanming Hu

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    Method of forming DRAM capactiors with protected outside crown surface for more robust structures
    2.
    发明申请
    Method of forming DRAM capactiors with protected outside crown surface for more robust structures 有权
    用于形成具有受保护的外表冠表面的DRAM盖板的方法用于更坚固的结构

    公开(公告)号：US20050179076A1

    公开(公告)日：2005-08-18

    申请号：US11098112

    申请日：2005-04-04

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    Method of forming DRAM capacitors with protected outside crown surface for more robust structures
    3.
    发明授权
    Method of forming DRAM capacitors with protected outside crown surface for more robust structures 有权
    形成具有受保护的外冠表面的DRAM电容器的方法用于更坚固的结构

    公开(公告)号：US06875655B2

    公开(公告)日：2005-04-05

    申请号：US10802564

    申请日：2004-03-17

    申请人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    发明人： Chun-Chieh Lin ,  Lan-Lin Chao ,  Chia-Hui Lin ,  Fu-Liang Yang ,  Chia-Shiung Tsai ,  Chanming Hu

    IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/10817 ,  H01L28/91

    摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.

    摘要翻译： 实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。 该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。 在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。 然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案以在电容器之间提供保护性层间电介质结构。 保护结构可防止在后续处理期间损坏底部电极。 蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。 在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement
    6.
    发明授权
    Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement 有权
    应变平衡结构具有拉伸应变硅通道和压缩应变硅 - 锗通道，用于CMOS性能提升

    公开(公告)号：US06955952B2

    公开(公告)日：2005-10-18

    申请号：US10383709

    申请日：2003-03-07

    申请人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    发明人： Yee-Chia Yeo ,  Chun-Chieh Lin ,  Fu-Liang Yang ,  Mong-Song Liang ,  Chenming Hu

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L27/12 ,  H01L31/109

    CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203

    摘要： A method of fabricating a CMOS device wherein mobility enhancement of both the NMOS and PMOS elements is realized via strain induced band structure modification, has been developed. The NMOS element is formed featuring a silicon channel region under biaxial strain while the PMOS element is simultaneously formed featuring a SiGe channel region under biaxial compressive strain. A novel process sequence allowing formation of a thicker silicon layer overlying a SiGe layer, allows the NMOS channel region to exist in the silicon layer which is under biaxial tensile stain enhancing electron mobility. The same novel process sequence results in the presence of a thinner silicon layer, overlying the same SiGe layer in the PMOS region, allowing the PMOS channel region to exist in the biaxial compressively strained SiGe layer, resulting in hole mobility enhancement.

    摘要翻译： 已经开发了通过应变诱导带结构修改来实现NMOS和PMOS元件的迁移率增强的CMOS器件的制造方法。 NMOS元件形成为具有双轴应变下的硅沟道区，同时形成在双轴压缩应变下具有SiGe沟道区的PMOS元件。 允许形成覆盖SiGe层的较厚硅层的新颖工艺顺序允许NMOS沟道区存在于双轴拉伸污染增强电子迁移率的硅层中。 相同的新工艺序列导致存在较薄的硅层，覆盖PMOS区域中相同的SiGe层，允许PMOS沟道区存在于双轴压缩应变SiGe层中，导致空穴迁移率增强。

    Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer
    7.
    发明授权
    Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer 有权
    使用应变硅锗层的选择性外延的互补金属氧化物半导体晶体管技术

    公开(公告)号：US06703271B2

    公开(公告)日：2004-03-09

    申请号：US10002031

    申请日：2001-11-30

    申请人： Yee-Chia Yeo ,  Chun Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

    发明人： Yee-Chia Yeo ,  Chun Chieh Lin ,  Fu-Liang Yang ,  Chen Ming Hu

    IPC分类号： H01L218238

    CPC分类号： H01L21/28167 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28114 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7846

    摘要： A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

    摘要翻译： 已经开发了用于制造具有包含应变SiGe层的沟道区的CMOS器件的工艺。 该工艺的特点是在N阱和P阱区的顶表面上复合硅层的选择性生长。 复合硅层由夹在选择性生长的未掺杂硅层之间的薄的应变SiGe层组成。 SiGe层中Ge的含量在约20至40重量％之间，允许存在增加的载流子迁移率而不产生硅缺陷。 薄的二氧化硅栅极绝缘体从选择性地生长的硅层的顶部热生长，位于覆盖选择性生长的SiGe层上。

    Semiconductor device with high-k gate dielectric
    10.
    发明申请
    Semiconductor device with high-k gate dielectric 有权
    具有高k栅极电介质的半导体器件

    公开(公告)号：US20050035345A1

    公开(公告)日：2005-02-17

    申请号：US10832020

    申请日：2004-04-26

    申请人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

    发明人： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

    IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/06

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

    摘要翻译： 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。