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    Socket structure stack and socket structure thereof
    1.
    发明授权
    Socket structure stack and socket structure thereof 有权
    套接字结构堆栈和套接字结构

    公开(公告)号：US08172622B1

    公开(公告)日：2012-05-08

    申请号：US13183595

    申请日：2011-07-15

    申请人： Chun-Ming Huang ,  Hui-Ming Lin ,  Chih-Chyau Yang ,  Chien-Ming Wu ,  Shih-Lun Chen

    发明人： Chun-Ming Huang ,  Hui-Ming Lin ,  Chih-Chyau Yang ,  Chien-Ming Wu ,  Shih-Lun Chen

    IPC分类号： H01R13/502

    CPC分类号： H01L25/0655 ,  H01L23/13 ,  H01L23/49827 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2225/1052 ,  H01L2225/1064 ,  H01R13/2435 ,  H05K1/144 ,  H05K3/284 ,  H05K2201/042 ,  H05K2201/10325 ,  H05K2201/10378

    摘要： A socket structure stack and a socket structure thereof are provided. The socket structure stack includes at least two socket structures, and each socket structure includes a main body, a plurality of conductive elements, and a plurality of connecting elements. The main body includes an inner plate and an outer plate, wherein the inner plate has a receiving portion and an embedded portion. The conductive elements are embedded in the embedded portion, and the connecting elements are mounted on the outer plate so as to connect adjacent socket structures together. The socket structures are so configured that ICs, processors, and printed circuit boards connected to the socket structures or the socket structures themselves can be recycled. Moreover, the printed circuit boards can be easily assembled to the socket structures, and the socket structures can be stacked up and securely connected to form a 3D structure which is otherwise difficult to put together by soldering.

    摘要翻译： 提供了一种插座结构堆叠及其插座结构。 插座结构堆叠包括至少两个插座结构，并且每个插座结构包括主体，多个导电元件和多个连接元件。 主体包括内板和外板，其中内板具有接收部分和嵌入部分。 导电元件嵌入在嵌入部分中，并且连接元件安装在外板上，以将相邻的插座结构连接在一起。 插座结构被配置成使得连接到插座结构或插座结构本身的IC，处理器和印刷电路板可以被再循环。 此外，印刷电路板可以容易地组装到插座结构上，并且插座结构可以堆叠并牢固地连接以形成否则难以通过焊接放在一起的3D结构。

    Three-dimensional SoC structure formed by stacking multiple chip modules
    2.
    发明授权
    Three-dimensional SoC structure formed by stacking multiple chip modules 有权
    通过堆叠多个芯片模块形成的三维SoC结构

    公开(公告)号：US08274794B2

    公开(公告)日：2012-09-25

    申请号：US12752345

    申请日：2010-04-01

    申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    IPC分类号： H05K7/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

    摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES
    6.
    发明申请
    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES 有权
    通过堆叠多个芯片模块形成的三维SOC结构

    公开(公告)号：US20110188210A1

    公开(公告)日：2011-08-04

    申请号：US12752345

    申请日：2010-04-01

    申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    IPC分类号： H05K1/14 ,  H05K7/00

    CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

    摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    Vehicle idle-speed warning system and idle-speed detection method
    7.
    发明授权
    Vehicle idle-speed warning system and idle-speed detection method 有权
    车辆怠速预警系统和怠速检测方法

    公开(公告)号：US09291115B2

    公开(公告)日：2016-03-22

    申请号：US13594615

    申请日：2012-08-24

    申请人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Chun-Yu Chen ,  Chien-Ming Wu

    发明人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Chun-Yu Chen ,  Chien-Ming Wu

    IPC分类号： G06G7/70 ,  G06G7/78 ,  F02D41/08 ,  G01C21/16 ,  F02D41/24 ,  F02D41/22

    CPC分类号： F02D41/08 ,  F02D41/2403 ,  F02D2041/228 ,  F02D2200/501 ,  F02D2200/701 ,  G01C21/16

    摘要： A vehicle idle-speed warning system and vehicle idle-speed detection method thereof are provided. It is non-invasive, that is, there is no need to change or modify any part of the constructing parts in the engine compartment. The present invention can be adopted stand-alone, or be applied to existing popular apparatuses, such as GPS, driving recorders, smart handheld devices, and vehicle electronic equipments. With the composing elements of a motion information module, an input module, an output module, a timer module and an information processing module, the present invention can accurately determine whether the vehicle under surveillance is in idle state and for how long it is in the idle state, and send an alarm signal automatically. With the implementation of the present invention, drivers can always be alarmed with the vehicle idling situations to prevent possible dangers or coming tickets due to the violation of traffic regulations in certain countries.

    摘要翻译： 提供了一种车辆怠速预警系统和车辆怠速检测方法。 这是非侵入性的，也就是说，不需要更改或修改发动机舱中构造部件的任何部分。 本发明可以单独使用，也可以应用于GPS，驾驶记录器，智能手持装置，车载电子设备等现有的流行装置。 利用运动信息模块，输入模块，输出模块，定时器模块和信息处理模块的组成元件，本发明可以准确地确定被监视的车辆是否处于空闲状态以及在多长时间内 空闲状态，并自动发送报警信号。 随着本发明的实施，驾驶员总是可以用车辆空转情况来警惕，以防止在某些国家因违反交通规则而导致的可能的危险或来车。

    Multi-project system-on-chip and its method
    8.
    发明授权
    Multi-project system-on-chip and its method 失效
    多项目片上系统及其方法

    公开(公告)号：US07571414B2

    公开(公告)日：2009-08-04

    申请号：US11453103

    申请日：2006-06-15

    申请人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

    发明人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/66

    摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

    摘要翻译： 通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统 因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。 此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程 从而得出。

    Multi-project system-on-chip and its method
    9.
    发明申请
    Multi-project system-on-chip and its method 失效
    多项目片上系统及其方法

    公开(公告)号：US20070294658A1

    公开(公告)日：2007-12-20

    申请号：US11453103

    申请日：2006-06-15

    申请人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

    发明人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F2217/66

    摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

    摘要翻译： 通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统 因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。 此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程 从而得出。