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    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES
    1.
    发明申请
    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES 有权
    通过堆叠多个芯片模块形成的三维SOC结构

    公开(公告)号：US20110188210A1

    公开(公告)日：2011-08-04

    申请号：US12752345

    申请日：2010-04-01

    申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    IPC分类号： H05K1/14 ,  H05K7/00

    CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

    摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    Three-dimensional SoC structure formed by stacking multiple chip modules
    4.
    发明授权
    Three-dimensional SoC structure formed by stacking multiple chip modules 有权
    通过堆叠多个芯片模块形成的三维SoC结构

    公开(公告)号：US08274794B2

    公开(公告)日：2012-09-25

    申请号：US12752345

    申请日：2010-04-01

    申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    IPC分类号： H05K7/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

    摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    UNITIZED CHARGING AND DISCHARGING BATTERY MANAGEMENT SYSTEM AND PROGRAMMABLE BATTERY MANAGEMENT MODULE THEREOF
    6.
    发明申请
    UNITIZED CHARGING AND DISCHARGING BATTERY MANAGEMENT SYSTEM AND PROGRAMMABLE BATTERY MANAGEMENT MODULE THEREOF 审中-公开
    电池充电和放电电池管理系统及其可编程电池管理模块

    公开(公告)号：US20110181245A1

    公开(公告)日：2011-07-28

    申请号：US12728288

    申请日：2010-03-22

    申请人： Chin-Long Wey ,  Chun-Ming Huang ,  Shih-Lun Chen ,  Chi-Sheng Lin ,  Ting-Hsu Chien ,  Jiann-Jenn Wang

    发明人： Chin-Long Wey ,  Chun-Ming Huang ,  Shih-Lun Chen ,  Chi-Sheng Lin ,  Ting-Hsu Chien ,  Jiann-Jenn Wang

    IPC分类号： H02J7/00

    CPC分类号： H02J7/0016 ,  H02J7/0019 ,  H02J7/0024 ,  Y02T10/7055

    摘要： The present invention discloses a unitized charging and discharging battery management system and a programmable battery management module thereof The unitized charging and discharging battery management system includes a smart battery module and a programmable battery management module, which has a universal loop and a control unit. The smart battery module has at least two smart batteries which are electrically connected by a plurality of switches and circuits of the universal loop to form a charging/discharging loop in series/parallel. The control unit monitors the charging and discharging status of the smart batteries to turn on or off the switches accordingly, so as to manage the smart batteries, thereby enhancing the overall power efficacy of the smart battery module. Besides, the service life of the smart battery module is also prolonged due to the simultaneous charging and discharging capability.

    摘要翻译： 本发明公开了一种单元化充放电电池管理系统及其可编程电池管理模块。该单元化充放电电池管理系统包括智能电池模块和可编程电池管理模块，其具有通用回路和控制单元。 智能电池模块具有至少两个智能电池，其通过多个开关和通用回路的电路电连接以形成串/并联的充电/放电回路。 控制单元监视智能电池的充电和放电状态，以相应地打开或关闭开关，以便管理智能电池，从而提高智能电池模块的整体功率效率。 此外，智能电池模块的使用寿命也由于同时的充放电能力而延长。

    CHIP STRUCTURE HAVING HISTORY RECORDING UNIT
    8.
    发明申请
    CHIP STRUCTURE HAVING HISTORY RECORDING UNIT 审中-公开
    具有历史记录单元的芯片结构

    公开(公告)号：US20130110465A1

    公开(公告)日：2013-05-02

    申请号：US13312219

    申请日：2011-12-06

    申请人： Chun-Ming Huang ,  Chi-Sheng Lin ,  Chien-Ming Wu

    发明人： Chun-Ming Huang ,  Chi-Sheng Lin ,  Chien-Ming Wu

    IPC分类号： G06F17/40

    CPC分类号： G01R31/2856 ,  G01R31/31707

    摘要： A chip structure having a history recording unit is provided. The chip structure includes a core circuit unit in addition to the history recording unit. The history recording unit includes a sensing unit, a record unit, and a deliver unit. The sensing unit detects the status of the core circuit unit and generates history information accordingly. The history information is saved into the record unit and can be further output by the deliver unit. Thus, the history information of the chip structure can be recorded and effectively used to eliminate the reliability problem of the chip structure.

    摘要翻译： 提供具有历史记录单元的芯片结构。 除了历史记录单元之外，芯片结构还包括核心电路单元。 历史记录单元包括感测单元，记录单元和传送单元。 感测单元检测核心电路单元的状态并相应地生成历史信息。 历史信息被保存到记录单元中，并且可以由传送单元进一步输出。 因此，可以记录和有效地利用芯片结构的历史信息来消除芯片结构的可靠性问题。

    Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same
    9.
    发明授权
    Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same 有权
    用于配置低复杂度LDPC解码器和低复杂度LDPC解码器的存储器的方法

    公开(公告)号：US08219879B2

    公开(公告)日：2012-07-10

    申请号：US12707848

    申请日：2010-02-18

    申请人： Chien-Ming Wu ,  Ming-Der Shieh ,  Chun-Ming Huang ,  Chi-Sheng Lin ,  Shih-Hao Fang ,  Shing-Chung Tang

    发明人： Chien-Ming Wu ,  Ming-Der Shieh ,  Chun-Ming Huang ,  Chi-Sheng Lin ,  Shih-Hao Fang ,  Shing-Chung Tang

    IPC分类号： H03M13/00 ,  G11C29/00 ,  G06F11/00

    CPC分类号： H03M13/116 ,  H03M13/1137 ,  H03M13/6505 ,  H03M13/6566

    摘要： A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.

    摘要翻译： 提供了一种用于使用相同方法来布置低复杂度低密度奇偶校验（LDPC）解码器和低复杂度LDPC解码器的存储器的方法。 用于布置低复杂度LDPC解码器的存储器的方法的主要思想是将至少一个或两个小容量存储器块合并到一个存储器组中，使得存储器区域可以减少，读取或写入中的功耗 数据降低。 此外，由于合并的存储器组在读取或写入数据时共享相同的地址线，所以使用至少一个延迟单元来调整读取或写入顺序，从而确保数据的有效性。 使用所公开的方法的低复杂度LDPC解码器可以满足高处理速率和低功耗的需求。

    MICROPARTICLE DETECTING APPARATUS
    10.
    发明申请
    MICROPARTICLE DETECTING APPARATUS 有权
    微波检测装置

    公开(公告)号：US20130291628A1

    公开(公告)日：2013-11-07

    申请号：US13547061

    申请日：2012-07-12

    申请人： Chun-ming Huang ,  Chen-chia Chen ,  Chi-Sheng Lin ,  Chien-ming Wu

    发明人： Chun-ming Huang ,  Chen-chia Chen ,  Chi-Sheng Lin ,  Chien-ming Wu

    IPC分类号： G01N33/49 ,  G01N21/85 ,  G01N27/74

    CPC分类号： G01N21/85 ,  G01N15/0272 ,  G01N2015/0065 ,  G01N2021/8571

    摘要： A microparticle detecting apparatus is disclosed and includes at least one detection unit, each of which includes: a first sieve having at least a first mesh, a separator stacked on one side of the first sieve and having a separator hole, and a second sieve stacked on one side of the separator and having several second meshes. The diameter of the second mesh is smaller than that of the first mesh, and the first and second meshes are misaligned with each other in a vertical direction of the first and second sieves. The detection unit further includes at least a sensor aligned with the first or second mesh for detecting microparticles trapping into the first mesh or passing through the second mesh. Therefore, the microparticle detecting apparatus is suitably used for detecting or counting any microparticles with different size, to effectively shorten the detection processes of sample fluids.

    摘要翻译： 公开了一种微粒检测装置，包括至少一个检测单元，每个检测单元包括：具有至少第一筛网的第一筛网，堆叠在第一筛子的一侧上并具有分隔件孔的隔板，以及堆叠的第二筛 在分离器的一侧并具有多个第二网格。 第二网格的直径小于第一网格的直径，并且第一和第二网格在第一和第二筛网的垂直方向上彼此不对准。 检测单元还包括至少一个与第一或第二网格对准的传感器，用于检测捕获到第一网孔中的微粒或通过第二网孔。 因此，微粒检测装置适合用于检测或计数不同尺寸的微粒，以有效地缩短样品流体的检测过程。