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    Socket structure stack and socket structure thereof
    1.
    发明授权
    Socket structure stack and socket structure thereof 有权
    套接字结构堆栈和套接字结构

    公开(公告)号：US08172622B1

    公开(公告)日：2012-05-08

    申请号：US13183595

    申请日：2011-07-15

    申请人： Chun-Ming Huang ,  Hui-Ming Lin ,  Chih-Chyau Yang ,  Chien-Ming Wu ,  Shih-Lun Chen

    发明人： Chun-Ming Huang ,  Hui-Ming Lin ,  Chih-Chyau Yang ,  Chien-Ming Wu ,  Shih-Lun Chen

    IPC分类号： H01R13/502

    CPC分类号： H01L25/0655 ,  H01L23/13 ,  H01L23/49827 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2225/1052 ,  H01L2225/1064 ,  H01R13/2435 ,  H05K1/144 ,  H05K3/284 ,  H05K2201/042 ,  H05K2201/10325 ,  H05K2201/10378

    摘要： A socket structure stack and a socket structure thereof are provided. The socket structure stack includes at least two socket structures, and each socket structure includes a main body, a plurality of conductive elements, and a plurality of connecting elements. The main body includes an inner plate and an outer plate, wherein the inner plate has a receiving portion and an embedded portion. The conductive elements are embedded in the embedded portion, and the connecting elements are mounted on the outer plate so as to connect adjacent socket structures together. The socket structures are so configured that ICs, processors, and printed circuit boards connected to the socket structures or the socket structures themselves can be recycled. Moreover, the printed circuit boards can be easily assembled to the socket structures, and the socket structures can be stacked up and securely connected to form a 3D structure which is otherwise difficult to put together by soldering.

    摘要翻译： 提供了一种插座结构堆叠及其插座结构。 插座结构堆叠包括至少两个插座结构，并且每个插座结构包括主体，多个导电元件和多个连接元件。 主体包括内板和外板，其中内板具有接收部分和嵌入部分。 导电元件嵌入在嵌入部分中，并且连接元件安装在外板上，以将相邻的插座结构连接在一起。 插座结构被配置成使得连接到插座结构或插座结构本身的IC，处理器和印刷电路板可以被再循环。 此外，印刷电路板可以容易地组装到插座结构上，并且插座结构可以堆叠并牢固地连接以形成否则难以通过焊接放在一起的3D结构。

    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES
    4.
    发明申请
    THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES 有权
    通过堆叠多个芯片模块形成的三维SOC结构

    公开(公告)号：US20110188210A1

    公开(公告)日：2011-08-04

    申请号：US12752345

    申请日：2010-04-01

    申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    IPC分类号： H05K1/14 ,  H05K7/00

    CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

    摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    Three-dimensional SoC structure formed by stacking multiple chip modules
    5.
    发明授权
    Three-dimensional SoC structure formed by stacking multiple chip modules 有权
    通过堆叠多个芯片模块形成的三维SoC结构

    公开(公告)号：US08274794B2

    公开(公告)日：2012-09-25

    申请号：US12752345

    申请日：2010-04-01

    申请人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    发明人： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

    IPC分类号： H05K7/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

    摘要： A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

    摘要翻译： 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

    UNITIZED CHARGING AND DISCHARGING BATTERY MANAGEMENT SYSTEM AND PROGRAMMABLE BATTERY MANAGEMENT MODULE THEREOF
    7.
    发明申请
    UNITIZED CHARGING AND DISCHARGING BATTERY MANAGEMENT SYSTEM AND PROGRAMMABLE BATTERY MANAGEMENT MODULE THEREOF 审中-公开
    电池充电和放电电池管理系统及其可编程电池管理模块

    公开(公告)号：US20110181245A1

    公开(公告)日：2011-07-28

    申请号：US12728288

    申请日：2010-03-22

    申请人： Chin-Long Wey ,  Chun-Ming Huang ,  Shih-Lun Chen ,  Chi-Sheng Lin ,  Ting-Hsu Chien ,  Jiann-Jenn Wang

    发明人： Chin-Long Wey ,  Chun-Ming Huang ,  Shih-Lun Chen ,  Chi-Sheng Lin ,  Ting-Hsu Chien ,  Jiann-Jenn Wang

    IPC分类号： H02J7/00

    CPC分类号： H02J7/0016 ,  H02J7/0019 ,  H02J7/0024 ,  Y02T10/7055

    摘要： The present invention discloses a unitized charging and discharging battery management system and a programmable battery management module thereof The unitized charging and discharging battery management system includes a smart battery module and a programmable battery management module, which has a universal loop and a control unit. The smart battery module has at least two smart batteries which are electrically connected by a plurality of switches and circuits of the universal loop to form a charging/discharging loop in series/parallel. The control unit monitors the charging and discharging status of the smart batteries to turn on or off the switches accordingly, so as to manage the smart batteries, thereby enhancing the overall power efficacy of the smart battery module. Besides, the service life of the smart battery module is also prolonged due to the simultaneous charging and discharging capability.

    摘要翻译： 本发明公开了一种单元化充放电电池管理系统及其可编程电池管理模块。该单元化充放电电池管理系统包括智能电池模块和可编程电池管理模块，其具有通用回路和控制单元。 智能电池模块具有至少两个智能电池，其通过多个开关和通用回路的电路电连接以形成串/并联的充电/放电回路。 控制单元监视智能电池的充电和放电状态，以相应地打开或关闭开关，以便管理智能电池，从而提高智能电池模块的整体功率效率。 此外，智能电池模块的使用寿命也由于同时的充放电能力而延长。

    Mixed voltage input/output buffer having low-voltage design
    8.
    发明授权
    Mixed voltage input/output buffer having low-voltage design 有权
    具有低电压设计的混合电压输入/输出缓冲器

    公开(公告)号：US07532034B2

    公开(公告)日：2009-05-12

    申请号：US11489325

    申请日：2006-07-19

    申请人： Ming-Dou Ker ,  Shih-Lun Chen

    发明人： Ming-Dou Ker ,  Shih-Lun Chen

    IPC分类号： H03K19/0175 ,  H03K19/00 ,  H03K10/02

    CPC分类号： H03K19/018528

    摘要： A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.

    摘要翻译： 具有低电压设计的混合电压输入/输出缓冲器包括预驱动器，跟踪单元，驱动单元和输入/输出垫，浮动井单元和传送单元。 预驱动器接收第一数据信号并使能信号并输出​​第一和第二数据电压。 跟踪单元提供Gate-Tracking功能。 驱动单元耦合预驱动器和跟踪单元，用于产生对应于第一数据电压的第一缓冲电压。 输入/输出焊盘耦合驱动单元以输出第一缓冲电压并接收第二数据信号。 输出单元用于输出对应于第二数据信号的第二缓冲电压。 浮动单元耦合到驱动单元和输入/输出垫，以便输出第一缓冲电压并接收第二数据信号。 浮动井单元用于防止漏电流。

    Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device
    9.
    发明授权
    Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device 有权
    用于通过将时钟和读取控制信号定时调整到存储器件来减少读取等待时间的装置

    公开(公告)号：US09058898B1

    公开(公告)日：2015-06-16

    申请号：US14256998

    申请日：2014-04-21

    申请人： Ming-Jing Ho ,  Shih-Lun Chen ,  Yu-Ming Sun

    发明人： Ming-Jing Ho ,  Shih-Lun Chen ,  Yu-Ming Sun

    IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/4091

    CPC分类号： G11C11/4076 ,  G11C7/1066 ,  G11C11/4091

    摘要： The present invention discloses an efficient way to read data from a memory device by aligning an internal clock of the memory interface circuit with the read data strobe signal from the memory device by delaying the internal clock along with control signals for reading the memory device before transmitting them to the memory device, wherein the internal clock of the memory controller can sample the read data from the memory device directly without using a FIFO device between the internal clock and the read data strobe so as to reduce latency of reading data from the memory device. For example, the memory device can be a double-data-rate (DDR) DRAM device, and the control signals includes command and address signals of the DDR DRAM device.

    摘要翻译： 本发明公开了一种从存储器件读取数据的有效方式，通过将存储器接口电路的内部时钟与来自存储器件的读取数据选通信号进行对准，通过在发送之前延迟内部时钟以及用于读取存储器件的控制信号 它们到存储器件，其中存储器控制器的内部时钟可以直接从存储器件采样读取数据，而不需要在内部时钟和读取数据选通之间使用FIFO器件，从而减少从存储器件读取数据的等待时间 。 例如，存储器件可以是双数据速率（DDR）DRAM器件，并且控制信号包括DDR DRAM器件的命令和地址信号。

    Signal delay circuit and signal delay method
    10.
    发明授权
    Signal delay circuit and signal delay method 有权
    信号延迟电路和信号延迟方式

    公开(公告)号：US08779821B2

    公开(公告)日：2014-07-15

    申请号：US13480492

    申请日：2012-05-25

    申请人： Shih-Lun Chen ,  Ming-Jing Ho

    发明人： Shih-Lun Chen ,  Ming-Jing Ho

    IPC分类号： H03H11/26 ,  H03K5/13 ,  H03K5/135

    CPC分类号： H03K5/133 ,  H03K5/135 ,  H03K5/14

    摘要： A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

    摘要翻译： 一种信号延迟电路，包括：第一延迟级，用于延迟第一输入信号以产生第一延迟信号; 以及第二延迟级，用于与第一延迟级的延迟单元的一部分协作以延迟第一延迟信号以产生第二延迟信号。 所述信号延迟电路选择性地启动所述第一延迟级或所述第二延迟级的延迟级，其中所述信号延迟电路混合所述第一延迟信号和所述第二延迟信号以在所述第一延迟级和所述第二延迟阶段产生第一混合信号 舞台都启用了。