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    Semiconductor package and method for fabricating the same
    1.
    发明申请
    Semiconductor package and method for fabricating the same 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20090102063A1

    公开(公告)日：2009-04-23

    申请号：US12287936

    申请日：2008-10-14

    申请人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    发明人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    IPC分类号： H01L23/48 ,  H01L21/00

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.

    摘要翻译： 本发明提供一种半导体封装及其制造方法。 该方法包括：在金属载体上形成第一抗蚀剂层; 形成穿过所述第一抗蚀剂层的多个开口; 在所述开口中形成导电金属层; 去除第一抗蚀剂层; 用介电层覆盖具有导电金属层的金属载体; 在介电层中形成盲孔以暴露导电金属层的一部分; 在介电层上形成导电电路和在盲孔中的导电柱，使得导电电路经由导电柱电连接到导电金属层; 将至少一个芯片电连接到所述导电电路; 形成用于封装所述芯片和所述导电电路的密封剂; 并且去除金属载体，从而允许在没有芯片载体的情况下形成半导体封装。 给定导电柱，导电电路和导电金属层都有效地耦合到电介质层以防止分层。 此外，缩小盲孔通孔有助于制造工艺并降低制造成本。

    Chip carrier for accommodating passive component
    2.
    发明授权
    Chip carrier for accommodating passive component 有权
    用于容纳无源元件的芯片载体

    公开(公告)号：US06521997B1

    公开(公告)日：2003-02-18

    申请号：US10039268

    申请日：2002-01-02

    申请人： Chien-Ping Huang ,  Wei-Chen Tseng ,  Yu-Ting Lai

    发明人： Chien-Ping Huang ,  Wei-Chen Tseng ,  Yu-Ting Lai

    IPC分类号： H01L2348

    CPC分类号： H01L23/3121 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

    摘要： A chip carrier for accommodating a passive component is proposed, allowing at least a chip to be electrically connected to the chip carrier. At least a pair of spaced-apart solder pads are formed on the chip carrier in no interference with the electrical connection between the chip and the chip carrier. A passive component is bonded at its two ends onto the solder pads by solder paste that electrically connects the passive component to the chip carrier. A recessed portion formed between the pair of the solder pads, is associated with a bottom surface of the passive component to form a passage, allowing a resin material for encapsulating the passive component or the chip to pass through and fill the passage, whereby the filled passage can prevent bridging of the solder paste and short circuit of the passive component from occurrence, thereby making yield of fabricated products desirably improved.

    摘要翻译： 提出了用于容纳无源部件的芯片载体，至少使芯片电连接到芯片载体。 至少一对间隔开的焊盘形成在芯片载体上，不会干扰芯片和芯片载体之间的电连接。 无源元件的两端通过将无源部件与芯片载体电连接的焊膏焊接到焊盘上。 形成在所述一对焊盘之间的凹部与被动部件的底面相关联，以形成通道，允许用于封装被动部件或芯片的树脂材料通过并填充通道，由此填充 通过可以防止焊膏的桥接和被动部件的短路不发生，从而使制造产品的产量理想地提高。

    Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep
    5.
    发明授权
    Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep 有权
    具有改进的电线布置方案的线接半导体器件，用于最小化异常线扫

    公开(公告)号：US06441501B1

    公开(公告)日：2002-08-27

    申请号：US09678184

    申请日：2000-09-30

    申请人： Charles Tseng ,  Chin-Te Chen ,  Yu-Ting Lai ,  Chung-Pao Wang

    发明人： Charles Tseng ,  Chin-Te Chen ,  Yu-Ting Lai ,  Chung-Pao Wang

    IPC分类号： H01L2352

    CPC分类号： H01L24/85 ,  H01L21/565 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49179 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00

    摘要： A wire-bonded semiconductor device with an improved wire-arrangement scheme is proposed, which can help minimize abnormal wire sweep during encapsulation process. Among the bonding wires on the semiconductor device, those located in corners would be mostly susceptible to abnormal wire sweep, particularly a high-loop bonding wire that is located in immediate adjacency to a low-loop bonding wire located in one corner of the wire-bonded semiconductor device. To solve this problem, the low-loop bonding wire that is located in immediate adjacency to the sweep-susceptible high-loop bonding wire is erected substantially to the same loop height as the high-loop bonding wire, so that it can serve as a shield to the sweep-susceptible high-loop bonding wire against the flow of injected resin during encapsulation process, thus preventing abnormal wire sweep. Alternatively, if a pair of low-loop bonding wires are located in immediate adjacency to the sweep-susceptible high-loop bonding wire and are bonded to a common double-wire bond pad, these two low-loop bonding wires are arranged in an intercrossed manner, which can also help reduce the impact of the injected resin on the sweep-susceptible high-loop bonding wire, thus preventing abnormal wire sweep. The prevention of abnormal wire sweep allows the finished semiconductor device to be more assured in quality and reliability.

    摘要翻译： 提出了一种具有改进的布线方案的导线键合半导体器件，可以帮助最小化封装过程中的异常线扫。 在半导体器件中的接合线之中，位于拐角处的那些将主要容易受到异常的线扫，特别是位于与位于线的一个拐角处的低环路接合线紧邻的高环路接合线， 键合半导体器件。 为了解决这个问题，位于与扫描敏感的高回路接合线直接相邻的低环路接合线基本上竖立成与高环接合线相同的环高度，从而可以作为 在封装过程中屏蔽抗扫描敏感的高回路接合线，防止注入树脂的流动，从而防止异常的线扫。 或者，如果一对低环路接合线立即与扫描敏感的高环路接合线相邻并且被结合到公共双线接合焊盘，则这两个低环路接合线布置在交叉 方式，这也可以有助于减少喷射树脂对扫描敏感的高环接合线的影响，从而防止异常的线扫。 防止异常线扫使得成品半导体器件在质量和可靠性方面更加放心。

    COMPUTER INFORMATION DISPLAY METHOD AND COMPUTER SYSTEM USING THE SAME
    7.
    发明申请
    COMPUTER INFORMATION DISPLAY METHOD AND COMPUTER SYSTEM USING THE SAME 审中-公开
    计算机信息显示方法和使用该计算机的计算机系统

    公开(公告)号：US20120131493A1

    公开(公告)日：2012-05-24

    申请号：US13297278

    申请日：2011-11-16

    申请人： Yu-Ting Lai ,  Yi-Chang Chen ,  Chih-Chien Liu ,  Chih-Hsing Kang

    发明人： Yu-Ting Lai ,  Yi-Chang Chen ,  Chih-Chien Liu ,  Chih-Hsing Kang

    IPC分类号： G06F3/048

    CPC分类号： G06F11/328 ,  G06F1/3206

    摘要： A computer system and a computer information display method thereof are provided. In the method, a computer information management unit stores computer information of an application program in a storage unit. During a system login process of the computer system, a processing unit reads the computer information form the storage unit, and displays the computer information and a login dialog on a screen unit.

    摘要翻译： 提供了一种计算机系统及其计算机信息显示方法。 在该方法中，计算机信息管理单元将应用程序的计算机信息存储在存储单元中。 在计算机系统的系统登录过程中，处理单元从存储单元读取计算机信息，并在屏幕单元上显示计算机信息和登录对话。

    Conductive trace structure and semiconductor package having the conductive trace structure
    8.
    发明授权
    Conductive trace structure and semiconductor package having the conductive trace structure 有权
    导电迹线结构和具有导电迹线结构的半导体封装

    公开(公告)号：US07102222B2

    公开(公告)日：2006-09-05

    申请号：US10846427

    申请日：2004-05-14

    申请人： Kuan-Ting Kuo ,  Yu-Ting Lai ,  Chin-Chien Chiang

    发明人： Kuan-Ting Kuo ,  Yu-Ting Lai ,  Chin-Chien Chiang

    IPC分类号： H01L23/48

    CPC分类号： H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A conductive trace structure and a semiconductor package having the conductive trace structure are provided. A plurality of conductive traces are formed in and surrounding a chip mounting area on a substrate, for mounting a chip on the chip mounting area. Widened portions are formed on the conductive traces in the chip mounting area and at positions across a periphery of the chip mounting area, the widened portions having a line width larger than that of the rest part of the conductive traces. The widened portions of the conductive traces can sustain concentrated thermal stress from the peripheral area of the chip caused by mismatch in coefficient of thermal expansion between the chip and the substrate. This prevents the conductive traces that pass through the periphery of the chip mounting area from cracks or breaks due to the thermal stress, thereby improving the reliability and yield of the semiconductor package.

    摘要翻译： 提供具有导电迹线结构的导电迹线结构和半导体封装。 多个导电迹线形成在基板上并围绕芯片安装区域周围，用于将芯片安装在芯片安装区域上。 扩大部分形成在芯片安装区域中的导电迹线上并且在芯片安装区域的周边的位置处形成，所述加宽部分的线宽大于导电迹线的其余部分的线宽。 导电迹线的加宽部分可以由芯片和衬底之间的热膨胀系数不匹配引起来自芯片外围区域的集中的热应力。 这防止了通过芯片安装区域的周边的导电迹线由于热应力而被破裂或断裂，从而提高了半导体封装的可靠性和产量。

    Conductive trace structure and semiconductor package having the conductive trace structure
    10.
    发明申请
    Conductive trace structure and semiconductor package having the conductive trace structure 有权
    导电迹线结构和具有导电迹线结构的半导体封装

    公开(公告)号：US20050073038A1

    公开(公告)日：2005-04-07

    申请号：US10846427

    申请日：2004-05-14

    申请人： Kuan-Ting Kuo ,  Yu-Ting Lai ,  Chin-Chien Chiang

    发明人： Kuan-Ting Kuo ,  Yu-Ting Lai ,  Chin-Chien Chiang

    IPC分类号： H01L23/498 ,  H01L29/00

    CPC分类号： H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A conductive trace structure and a semiconductor package having the conductive trace structure are provided. A plurality of conductive traces are formed in and surrounding a chip mounting area on a substrate, for mounting a chip on the chip mounting area. Widened portions are formed on the conductive traces in the chip mounting area and at positions across a periphery of the chip mounting area, the widened portions having a line width larger than that of the rest part of the conductive traces. The widened portions of the conductive traces can sustain concentrated thermal stress from the peripheral area of the chip caused by mismatch in coefficient of thermal expansion between the chip and the substrate. This prevents the conductive traces that pass through the periphery of the chip mounting area from cracks or breaks due to the thermal stress, thereby improving the reliability and yield of the semiconductor package.

    摘要翻译： 提供具有导电迹线结构的导电迹线结构和半导体封装。 多个导电迹线形成在基板上并围绕芯片安装区域周围，用于将芯片安装在芯片安装区域上。 扩大部分形成在芯片安装区域中的导电迹线上并且在芯片安装区域的周边的位置处形成，所述加宽部分的线宽大于导电迹线的其余部分的线宽。 导电迹线的加宽部分可以由芯片和衬底之间的热膨胀系数不匹配引起来自芯片外围区域的集中的热应力。 这防止了通过芯片安装区域的周边的导电迹线由于热应力而被破裂或断裂，从而提高了半导体封装的可靠性和产量。