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    Semiconductor package and method for fabricating the same
    1.
    发明申请
    Semiconductor package and method for fabricating the same 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20090102063A1

    公开(公告)日：2009-04-23

    申请号：US12287936

    申请日：2008-10-14

    申请人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    发明人： Chun-Yuan Lee ,  Chien Ping Huang ,  Yu-Ting Lai ,  Cheng-Hsu Hsiao ,  Chun-Chi Ke

    IPC分类号： H01L23/48 ,  H01L21/00

    CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： This invention provides a semiconductor package and a method for fabricating the same. The method includes: forming a first resist layer on a metal carrier; forming a plurality of openings penetrating the first resist layer; forming a conductive metal layer in the openings; removing the first resist layer; covering the metal carrier having the conductive metal layer with a dielectric layer; forming blind vias in the dielectric layer to expose a portion of the conductive metal layer; forming conductive circuit on the dielectric layer and conductive posts in the blind vias, such that the conductive circuit is electrically connected to the conductive metal layer via the conductive posts; electrically connecting at least one chip to the conductive circuit; forming an encapsulant for encapsulating the chip and the conductive circuit; and removing the metal carrier, thereby allowing a semiconductor package to be formed without a chip carrier. Given the conductive posts, both the conductive circuit and conductive metal layer are efficiently coupled to the dielectric layer to prevent delamination. Further, downsizing the blind vias facilitates the fabrication process and cuts the fabrication cost.

    摘要翻译： 本发明提供一种半导体封装及其制造方法。 该方法包括：在金属载体上形成第一抗蚀剂层; 形成穿过所述第一抗蚀剂层的多个开口; 在所述开口中形成导电金属层; 去除第一抗蚀剂层; 用介电层覆盖具有导电金属层的金属载体; 在介电层中形成盲孔以暴露导电金属层的一部分; 在介电层上形成导电电路和在盲孔中的导电柱，使得导电电路经由导电柱电连接到导电金属层; 将至少一个芯片电连接到所述导电电路; 形成用于封装所述芯片和所述导电电路的密封剂; 并且去除金属载体，从而允许在没有芯片载体的情况下形成半导体封装。 给定导电柱，导电电路和导电金属层都有效地耦合到电介质层以防止分层。 此外，缩小盲孔通孔有助于制造工艺并降低制造成本。

    Semiconductor package with heat sink
    3.
    发明授权
    Semiconductor package with heat sink 有权
    半导体封装带散热片

    公开(公告)号：US07177155B2

    公开(公告)日：2007-02-13

    申请号：US11212290

    申请日：2005-08-26

    申请人： Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Ping Huang

    发明人： Chang-Fu Lin ,  Han-Ping Pu ,  Cheng-Hsu Hsiao ,  Chien Ping Huang

    IPC分类号： H05K7/20 ,  H01L23/34

    CPC分类号： H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/19105 ,  H01L2924/00014

    摘要： A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a plurality of grooves or holes at positions in contact with the substrate, allowing an adhesive material to be applied between the heat sink and the substrate and filled into the grooves or holes for attaching the heat sink onto the substrate. The adhesive material filled into the grooves or holes provides an anchoring effect for firmly positioning the heat sink on the substrate. Therefore, it is not necessary to form predetermined holes on the substrate for being coupled to fixing members such as bolts, and incorporation of the heat sink would not affect trace routability and arrangement of input/output connections such as solder balls on the substrate and would not lead to cracks of the chip.

    摘要翻译： 提供了具有散热器的半导体封装，其中至少一个芯片安装在基板上并被散热器覆盖。 散热器在与基板接触的位置处形成有多个凹槽或孔，允许将粘合材料施加在散热器和基板之间并填充到用于将散热器附接到基板上的凹槽或孔中。 填充到槽或孔中的粘合剂材料提供了将散热器牢固地定位在基板上的锚固效果。 因此，不需要在基板上形成预定的孔，用于连接诸如螺栓的固定构件，并且散热器的结合不会影响迹线布线性以及衬底上的诸如焊球的输入/输出连接的布置 不会导致芯片的裂纹。

    Integrated circuit package configuration having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body
    8.
    发明授权
    Integrated circuit package configuration having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body 有权
    集成电路封装结构，其具有带法兰部分的封装体和用于模制封装体的封装模具

    公开(公告)号：US06743706B2

    公开(公告)日：2004-06-01

    申请号：US10163060

    申请日：2002-06-05

    申请人： Chien Ping Huang

    发明人： Chien Ping Huang

    IPC分类号： H01L2144

    CPC分类号： H01L21/565 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

    摘要： An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body. This benefit allows the clamping force from the two molds to be reduced to a lower level; and therefore, it would not cause the undesired forming of micro-cracks in the substrate that would otherwise occur in the case of the prior art where a larger clamping force is required to prevent flash. The manufactured integrated circuit package is therefore more assured in quality and reliability. Moreover, the manufacture process can be more simplified to save manufacture cost.

    摘要翻译： 提出一种集成电路封装，其具有带凸缘部分的封装体和用于模制封装体的封装模具。 所提出的包封模具的特征在于，形成在上模具中的封装体腔体还包括在其边缘中的收缩的切口部分。收缩的切口部分可以是均匀的或者形成在多级阶梯式 像形状。 在模塑过程中，用于形成封装体的树脂将流入该收缩的切口部分; 并且在收缩的切口部分内，树脂将更快地吸收上模的热量，从而增加其粘度并延缓其流动速度。 结果，树脂不太可能闪烁到超过封装体的基板的那些表面部分上。 这个优点使得来自两个模具的夹紧力可以降低到较低的水平; 因此，在现有技术的情况下，如果需要较大的夹紧力来防止闪光，则不会导致在基板中不期望的形成微裂纹。 因此，制造的集成电路封装在质量和可靠性方面更加确保。 此外，制造过程可以更加简化以节省制造成本。

    Ball grid array semiconductor package with exposed base layer
    9.
    发明授权
    Ball grid array semiconductor package with exposed base layer 有权
    球栅阵列半导体封装，具有暴露的基极层

    公开(公告)号：US06528722B2

    公开(公告)日：2003-03-04

    申请号：US09235095

    申请日：1999-01-21

    申请人： Chien Ping Huang ,  Randy H. Y. Lo

    发明人： Chien Ping Huang ,  Randy H. Y. Lo

    IPC分类号： H01L2328

    CPC分类号： H05K13/0465 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

    摘要： A Ball Grid Array (BGA) semiconductor package with exposed base layer includes a base layer having an opening portion in the center thereof and formed with a plurality of holes about the opening portion. A plurality of leads are attached to a second surface of the base layer and each of the leads is connected to a corresponding hole in the base layer. A semiconductor chip is attached and electrically connected to the leads. The semiconductor chip and the leads are covered by an encapsulant formed by an encapsulating compound, leaving a first surface of the base layer exposed. A plurality of solder balls are planted in the holes in the base layer, which are electrically bonded to the leads so as to electrically connect the semiconductor chip to external devices. In this BGA semiconductor package, the leads together with the base layer are used as a substrate for the semiconductor chip to attach thereto. Therefore, there is no need of costly BGA substrate.

    摘要翻译： 具有暴露基层的球栅阵列（BGA）半导体封装包括在其中心具有开口部分并且围绕开口部分形成有多个孔的基层。 多个引线附接到基层的第二表面，并且每个引线连接到基层中的对应的孔。 半导体芯片被附接并电连接到引线。 半导体芯片和引线被由封装化合物形成的密封剂覆盖，留下基底层的第一表面露出。 多个焊球被种植在基底层的孔中，电焊接到引线上，以将半导体芯片电连接到外部装置。 在该BGA半导体封装中，将引线与基极层一起用作半导体芯片附着于其上的基板。 因此，不需要昂贵的BGA基板。