公开(公告)号：USD688229S1

公开(公告)日：2013-08-20

申请号：US29418991

申请日：2012-04-24

申请人： Dai Hyung Ryu ,  Ha Na Kim ,  Ho Young Joo ,  Min Jae Lee

设计人： Dai Hyung Ryu ,  Ha Na Kim ,  Ho Young Joo ,  Min Jae Lee

公开(公告)号：USD688228S1

公开(公告)日：2013-08-20

申请号：US29418987

申请日：2012-04-24

申请人： Dai Hyung Ryu ,  Min Jae Lee ,  Gang Ho Woo ,  Ha Na Kim ,  Ho Young Joo

设计人： Dai Hyung Ryu ,  Min Jae Lee ,  Gang Ho Woo ,  Ha Na Kim ,  Ho Young Joo

公开(公告)号：US09018743B2

公开(公告)日：2015-04-28

申请号：US13566082

申请日：2012-08-03

申请人： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

发明人： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

IPC分类号： H01L23/495 ,  H01L23/00 ,  H05K3/34 ,  H05K3/30 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/14133 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

摘要翻译： 提供一种半导体器件，其中当半导体管芯附接到电路板时，可以防止或显着减小半导体管芯和衬底（例如电路板）之间的偏移。 在非限制性示例中，半导体器件包括：包括至少一个凸块的半导体管芯; 以及电路板，其包括至少一个电路图案，所述凸块电连接到所述电路图案。 在非限制性示例中，电路板包括：绝缘层，包括中心区域和围绕中心区域的周边区域; 形成在所述绝缘层的中心区域中的多个中心电路图案; 以及形成在绝缘层的周边区域中的多个外围电路图案。 中心电路图案可以形成为比以Z字形图案形成的外围电路图形更宽，和/或可以形成为交叉形状。

公开(公告)号：US20140365456A1

公开(公告)日：2014-12-11

申请号：US14241193

申请日：2012-08-27

申请人： Min Jae Lee

发明人： Min Jae Lee

IPC分类号： G06F17/30

CPC分类号： G06F16/951 ,  G06F16/3347 ,  G06F16/335

摘要： Disclosed relates to a recommendation engine. The recommendation engine includes a query generation module configured to store a plurality of item vectors as a plurality of documents, configured to search for a reference document associated with the reference item among the plurality of the documents to extract a reference item vector and configured to generate a query including at least one user best associated with the extracted reference item vector if successful, each of the plurality of the item vectors corresponding to an element including a user-preference pair and a search module configured to calculate a correlation between the extracted reference item vector and each of the plurality of the item vectors in the plurality of the documents based on the generated query to provide the at least one recommendation item.

摘要翻译： 公开涉及推荐引擎。 所述推荐引擎包括查询生成模块，被配置为将多个项目向量存储为多个文档，被配置为搜索与所述多个文档中的所述参考项目相关联的参考文档，以提取参考项向量并且被配置为生成 如果成功，则包括与所提取的参考项向量最相关联的至少一个用户的查询，所述多个项目向量中的每一个对应于包括用户偏好对的元素和被配置为计算所提取的参考项目之间的相关性的搜索模块 基于所生成的查询，在所述多个文档中的所述多个项目向量中的每一个，以提供所述至少一个推荐项。

公开(公告)号：USD647905S1

公开(公告)日：2011-11-01

申请号：US29385276

申请日：2011-02-11

申请人： Min Jae Lee ,  Gang Ho Woo ,  Young Won Jeong

设计人： Min Jae Lee ,  Gang Ho Woo ,  Young Won Jeong

公开(公告)号：US07843052B1

公开(公告)日：2010-11-30

申请号：US12270690

申请日：2008-11-13

申请人： Min Yoo ,  Ki Wook Lee ,  Min Jae Lee

发明人： Min Yoo ,  Ki Wook Lee ,  Min Jae Lee

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/73259 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/81805

摘要： Semiconductor devices are disclosed. In an embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die. The stack of the second semiconductor dies is encapsulated by an encapsulant. Redistribution layers are formed on one surface of the stack and are connected to the through-silicon vias. Solder balls are attached to the respective redistribution layers. In another embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die formed with through-silicon vias. Redistribution layers are formed on the back surface of the first semiconductor die. Solder balls are attached to the respective redistribution layers. Further disclosed are methods for fabricating the semiconductor devices.

摘要翻译： 公开了半导体器件。 在一个实施例中，形成有穿硅通孔的多个第二半导体管芯被堆叠在第一半导体管芯上。 第二半导体管芯的堆叠由密封剂封装。 再分布层形成在堆叠的一个表面上并且连接到穿硅通孔。 焊球附着在相应的再分布层上。 在另一个实施例中，形成有穿硅通孔的多个第二半导体管芯被堆叠在形成有通孔硅通孔的第一半导体管芯上。 在第一半导体管芯的后表面上形成再分布层。 焊球附着在相应的再分布层上。 还公开了制造半导体器件的方法。

公开(公告)号：US09355981B2

公开(公告)日：2016-05-31

申请号：US13596322

申请日：2012-08-28

申请人： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

发明人： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

IPC分类号： H01L21/00 ,  H01L23/00 ,  H05K3/34 ,  H05K3/30 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/14133 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

公开(公告)号：US20130037945A1

公开(公告)日：2013-02-14

申请号：US13596322

申请日：2012-08-28

申请人： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

发明人： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

IPC分类号： H05K1/02 ,  H01L23/48

CPC分类号： H01L24/17 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/14133 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

摘要： Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

摘要翻译： 提供一种半导体器件，其中当半导体管芯附接到电路板时，可以防止或显着减小半导体管芯和衬底（例如电路板）之间的偏移。 在非限制性示例中，半导体器件包括：包括至少一个凸块的半导体管芯; 以及电路板，其包括至少一个电路图案，所述凸块电连接到所述电路图案。 在非限制性示例中，电路板包括：绝缘层，包括中心区域和围绕中心区域的周边区域; 形成在所述绝缘层的中心区域中的多个中心电路图案; 以及形成在绝缘层的周边区域中的多个外围电路图案。 中心电路图案可以形成为比以Z字形图案形成的外围电路图形更宽，和/或可以形成为交叉形状。

公开(公告)号：US08089148B1

公开(公告)日：2012-01-03

申请号：US12539116

申请日：2009-08-11

申请人： Jun Su Lee ,  Min Jae Lee ,  Jae Dong Kim ,  Jae Jin Lee ,  Min Yoo ,  Byung Jun Kim

发明人： Jun Su Lee ,  Min Jae Lee ,  Jae Dong Kim ,  Jae Jin Lee ,  Min Yoo ,  Byung Jun Kim

IPC分类号： H01L23/48

CPC分类号： H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/32225 ,  H01L2924/00012

摘要： A circuit board has an insulative layer including a first surface and a second surface opposite to the first surface. A plurality of electrically conductive patterns is formed on the first surface of the insulative layer. Conductive lands are formed in a die mounting region of the first surface of the insulative layer and electrically connected to one of the plurality of conductive patterns on the first surface. An extending pattern extends from the conductive lands to outside of the mounting region. A protective layer covers the first surface of the insulative layer and the electrically conductive patterns. A trench is formed in the protective layer to expose the conductive lands and the extending patterns.

摘要翻译： 电路板具有包括与第一表面相对的第一表面和第二表面的绝缘层。 在绝缘层的第一表面上形成多个导电图案。 导电焊盘形成在绝缘层的第一表面的管芯安装区域中，并且与第一表面上的多个导电图案之一电连接。 延伸图案从导电焊盘延伸到安装区域的外部。 保护层覆盖绝缘层的第一表面和导电图案。 在保护层中形成沟槽以暴露导电焊盘和延伸图案。

公开(公告)号：USD617795S1

公开(公告)日：2010-06-15

申请号：US29337005

申请日：2009-05-13

申请人： Min Ji Seo ,  Min Jae Lee

设计人： Min Ji Seo ,  Min Jae Lee