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143 条记录 (耗时 0.123 秒)

    Movable terminal in a two terminal memory array
    1.
    发明授权
    Movable terminal in a two terminal memory array 失效
    两个终端存储器阵列中的可移动终端

    公开(公告)号：US07701834B2

    公开(公告)日：2010-04-20

    申请号：US11037971

    申请日：2005-01-18

    申请人： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    发明人： Darrell Rinerson ,  Christophe Chevallier ,  John E. Sanchez, Jr. ,  Lawerence Schloss

    IPC分类号： G11B9/00

    CPC分类号： G11B9/08 ,  B82Y10/00 ,  G11B9/1445

    摘要： A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

    摘要翻译： 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
    7.
    发明授权
    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
    本地位线及其选择方法可以访问交叉点阵列中的存储器元件

    公开(公告)号：US08270193B2

    公开(公告)日：2012-09-18

    申请号：US12657911

    申请日：2010-01-29

    申请人： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

    发明人： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    摘要翻译： 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
    9.
    发明申请
    Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
    本地位线及其选择方法可以访问交叉点阵列中的存储器元件

    公开(公告)号：US20110188281A1

    公开(公告)日：2011-08-04

    申请号：US12657911

    申请日：2010-01-29

    申请人： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    发明人： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Namala

    IPC分类号： G11C5/02 ,  G11C11/00 ,  G11C8/00 ,  H01L21/82

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/77 ,  H01L21/82 ,  H01L27/2481 ,  H01L45/16

    摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

    摘要翻译： 实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。 在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。 交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。 每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。 还包括设置在X线的子集和Y线部分的组之间的存储器元件。 在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。