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公开(公告)号：US07889539B2
公开(公告)日：2011-02-15
申请号：US12653486
申请日：2009-12-14
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
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公开(公告)号：US07326979B2
公开(公告)日：2008-02-05
申请号：US10665882
申请日：2003-09-19
申请人： Darrell Rinerson , Wayne Kinney , John E. Sanchez, Jr. , Steven W. Longcor , Steve Kuo-Ren Hsia , Edmond Ward , Christophe Chevallier
发明人： Darrell Rinerson , Wayne Kinney , John E. Sanchez, Jr. , Steven W. Longcor , Steve Kuo-Ren Hsia , Edmond Ward , Christophe Chevallier
IPC分类号： H01L29/76
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2418 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/165
摘要： A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.
摘要翻译： 提供了使用处理接口的多电阻状态元素。 存储插头包括夹着多电阻状态元件的至少两个电极。 在电极/多电阻状态元件接口上使用不同的处理可改善整个存储器件的存储器特性。
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公开(公告)号：US07082052B2
公开(公告)日：2006-07-25
申请号：US10773549
申请日：2004-02-06
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/14
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。
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公开(公告)号：US07394679B2
公开(公告)日：2008-07-01
申请号：US11473005
申请日：2006-06-22
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： G11C11/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。
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公开(公告)号：US08062942B2
公开(公告)日：2011-11-22
申请号：US12215958
申请日：2008-06-30
申请人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人： Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe J. Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号： H01L21/00
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。
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公开(公告)号：US07186569B2
公开(公告)日：2007-03-06
申请号：US10605977
申请日：2003-11-11
申请人： Darrell Rinerson , Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor , Emond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven W. Longcor , Emond Ward
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.
摘要翻译： 提供导电存储器堆叠。 存储器堆叠包括底部电极，顶部电极和多电阻状态元件。 多电阻状态元件被夹在电极之间，使得底部电极的顶面与多电阻状态元件的底面接触，并且顶部电极的底面与多电阻状态元件的底面接触 顶面。 底部电极，顶部电极和多电阻状态元件都具有与其表面相邻的侧面。 此外，侧面至少部分地被侧壁层覆盖。
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公开(公告)号：US07884349B2
公开(公告)日：2011-02-08
申请号：US12283339
申请日：2008-09-11
申请人： Darrell Rinerson , Steve Kuo-Ren Hsia , Steven W. Longcor , Wayne Kinney , Edmond Ward , Christophe J. Chevallier
发明人： Darrell Rinerson , Steve Kuo-Ren Hsia , Steven W. Longcor , Wayne Kinney , Edmond Ward , Christophe J. Chevallier
IPC分类号： H01L29/06
CPC分类号： H01L27/101 , G11C11/00 , G11C11/56 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/77 , G11C2213/79 , H01L27/11502 , H01L27/11507 , H01L27/24 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/00 , H01L45/10 , H01L45/1233 , H01L45/147
摘要： A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a semiconductor based selection device operative to electrically isolate the memory element from a range of voltages applied across the memory cell that are not read voltages operative read stored data from the memory element or write voltages operative to write data to the memory element. The selection device may comprise a pair of diodes that are electrically in series with each other and disposed in a back-to-back configuration. The memory cell may be fabricated over a substrate (e.g., a silicon wafer) that includes active circuitry. The selection device and the semiconductor materials (e.g., poly-silicon) that form the selection device are fabricated above the substrate and are integrated with other thin film layers of material that form the memory cell.
摘要翻译： 公开了一种包括彼此电串联的存储元件和非欧姆器件（NOD）的存储单元。 NOD包括基于半导体的选择装置，其操作以将存储器元件与施加在存储器单元上的电压范围电隔离，所述电压范围不是读取电压，从存储元件读取存储的数据，或者写入电压可操作以将数据写入存储器元件。 选择装置可以包括彼此电连接并以背对背配置设置的一对二极管。 可以在包括有源电路的衬底（例如，硅晶片）上制造存储器单元。 形成选择装置的选择装置和半导体材料（例如，多晶硅）制造在衬底之上，并与形成存储单元的材料的其它薄膜层集成。
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公开(公告)号：US08675389B2
公开(公告)日：2014-03-18
申请号：US13272985
申请日：2011-10-13
申请人： Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez, Jr. , Philip Swab , Edmond Ward
发明人： Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , Darrell Rinerson , John Sanchez, Jr. , Philip Swab , Edmond Ward
IPC分类号： G11C11/21
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
摘要翻译： 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。
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公开(公告)号：US08611130B2
公开(公告)日：2013-12-17
申请号：US13301490
申请日：2011-11-21
申请人： Darrell Rinerson , Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , John Sanchez, Jr. , Philip Swab , Edmond Ward
发明人： Darrell Rinerson , Christophe Chevallier , Steve Kuo-Ren Hsia , Wayne Kinney , Steven Longcor , John Sanchez, Jr. , Philip Swab , Edmond Ward
CPC分类号： H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要： A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译： 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属（或非常薄的材料层）通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性，这在某些阵列中是有利的。
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公开(公告)号：US06972985B2
公开(公告)日：2005-12-06
申请号：US10868578
申请日：2004-06-15
申请人： Darrell Rinerson , Christophe J. Chevallier , Philip F. S. Swab , Steve Kuo-Ren Hsia , John E. Sanchez, Jr. , Steven W. Longcor
发明人： Darrell Rinerson , Christophe J. Chevallier , Philip F. S. Swab , Steve Kuo-Ren Hsia , John E. Sanchez, Jr. , Steven W. Longcor
CPC分类号： G11C13/0011 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/77 , G11C2213/79
摘要： A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.
摘要翻译： 提供了包括具有岛的存储元件的存储器。 存储器具有地址解码电路和一组存储器插头。 存储器插头包括在第二材料的主体内具有第一材料的岛结构的存储元件。 岛结构通常是纳米颗粒。 存储器插头可以以第一写入电压处于第一电阻状态，以第二写入电压置于第二电阻状态，并且在读取电压下确定其电阻状态。
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