公开(公告)号：US5310690A

公开(公告)日：1994-05-10

申请号：US880477

申请日：1992-05-06

申请人： David A. Bell ,  Robert H. Havemann

发明人： David A. Bell ,  Robert H. Havemann

IPC分类号： H01L21/74 ,  H01L21/8249 ,  H01L21/265

CPC分类号： H01L21/8249 ,  H01L21/74

摘要： A method for fabricating an integrated circuit having a buried doped region is disclosed. A thermal oxide layer is formed over a portion of a p-type substrate at which an n+ buried doped region is not to be formed, masking the implant for the buried doped region. Anneal of the implant is performed in an oxidizing atmosphere, growing further oxide over the surface. The oxide layers are removed, and a p-type blanket implant is performed for isolation purposes and, if desired, to form a p-type buried doped region; the doping concentration of the n+ buried doped region retards diffusion of the boron to the surface thereover. Alternatively, a higher than normal doping level in the substrate can provide sufficient boron for isolation. An epitaxial layer is then grown over the surface, and the n-well is formed by implanting n-type dopant, with the p-well regions masked by a nitride mask; anneal of the n-well is also done in an oxidizing environment, so that consumption of a portion of the n-well by the oxide further planarizes the topography of the device.

摘要翻译： 公开了一种制造具有掩埋掺杂区域的集成电路的方法。 在不需要形成n +掩埋掺杂区域的p型衬底的一部分上形成热氧化物层，掩蔽埋入掺杂区域的注入。 植入物的退火在氧化气氛中进行，在表面上进一步生长氧化物。 去除氧化物层，并且为了隔离目的进行p型覆盖注入，并且如果需要，进行p型掩埋掺杂区域的形成; n +掩埋掺杂区域的掺杂浓度阻碍硼向其表面的扩散。 或者，衬底中高于正常的掺杂水平可以提供足够的硼用于分离。 然后在表面上生长外延层，并且通过注入n型掺杂剂形成n阱，其中p阱区域被氮化物掩模掩蔽; n阱的退火也在氧化环境中进行，因此通过氧化物消耗n阱的一部分进一步平坦化了器件的形貌。

公开(公告)号：US5451530A

公开(公告)日：1995-09-19

申请号：US179849

申请日：1994-01-11

申请人： David A. Bell ,  Robert H. Havemann

发明人： David A. Bell ,  Robert H. Havemann

IPC分类号： H01L21/266 ,  H01L21/74 ,  H01L21/761

CPC分类号： H01L21/266 ,  H01L21/74

摘要： A method for fabricating an integrated circuit having a buried doped region is disclosed. A thermal oxide layer is formed over a portion of a p-type substrate at which an n+ buried doped region is not to be formed, masking the implant for the buried doped region. Anneal of the implant is performed in an oxidizing atmosphere, growing further oxide over the surface. The oxide layers are removed, and a p-type blanket implant is performed for isolation purposes and, if desired, to form a p-type buried doped region; the doping concentration of the n+ buried doped region retards diffusion of the boron to the surface thereover. Alternatively, a higher than normal doping level in the substrate can provide sufficient boron for isolation. An epitaxial layer is then grown over the surface, and the n-well is formed by implanting n-type dopant, with the p-well regions masked by a nitride mask; anneal of the n-well is also done in an oxidizing environment, so that consumption of a portion of the n-well by the oxide further planarizes the topography of the device.

摘要翻译： 公开了一种制造具有掩埋掺杂区域的集成电路的方法。 在不需要形成n +掩埋掺杂区域的p型衬底的一部分上形成热氧化物层，掩蔽埋入掺杂区域的注入。 植入物的退火在氧化气氛中进行，在表面上进一步生长氧化物。 去除氧化物层，并且为了隔离目的进行p型覆盖注入，并且如果需要，进行p型掩埋掺杂区域的形成; n +掩埋掺杂区域的掺杂浓度阻碍硼向其表面的扩散。 或者，衬底中高于正常的掺杂水平可以提供足够的硼用于分离。 然后在表面上生长外延层，并且通过注入n型掺杂剂形成n阱，其中p阱区域被氮化物掩模掩蔽; n阱的退火也在氧化环境中进行，因此通过氧化物消耗n阱的一部分进一步平坦化了器件的形貌。

公开(公告)号：US06995439B1

公开(公告)日：2006-02-07

申请号：US10803234

申请日：2004-03-17

申请人： Richard S. Hill ,  Willibrordus Gerardus Maria van den Hoek ,  Robert H. Havemann

发明人： Richard S. Hill ,  Willibrordus Gerardus Maria van den Hoek ,  Robert H. Havemann

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/7682 ,  H01L2221/1047

摘要： Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.

摘要翻译： 通过在致密电介质的预先形成的层中引入小的垂直或柱状间隙来产生多孔电介质层。 可以通过与用于在VLSI器件上形成金属线和其它特征的工艺不同的特殊工艺形成孔。 此外，在特定层的平坦化处理已经完成之后可以产生柱状间隙。 然后，在形成孔之后，通过沉积另一层材料来封盖它们。 以这种方式，保护新的多孔层免于直接暴露于随后的平坦化工艺的压力。 在替代实施例中，应用本文所述的工艺以将孔引入预成形的半导体层中以产生多孔半导体层。

公开(公告)号：US06365451B2

公开(公告)日：2002-04-02

申请号：US09821602

申请日：2001-03-29

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L218238

CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7322

摘要： A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.

摘要翻译： 一种制造半导体器件和器件的方法。 该器件通过提供具有导电材料之上的区域的基底和在导电材料区域上的电介质第一侧壁间隔物来制造。 第二侧壁间隔件形成在从相对于第一侧壁间隔件选择性地移除的材料延伸到基板的第一侧壁间隔物的上方。 形成接触第二侧壁间隔物并与衬底隔开的导电区域。 第二侧壁间隔件可选择性地移除以在基板和导电区域之间形成开口。 开口填充有导电材料以将导电材料电耦合到基底。

公开(公告)号：US06271577B1

公开(公告)日：2001-08-07

申请号：US09212136

申请日：1998-12-15

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L27082

CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7322

摘要： A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.

摘要翻译： 一种制造半导体器件和器件的方法。 该器件通过提供具有导电材料之上的区域的基底和在导电材料区域上的电介质第一侧壁间隔物来制造。 第二侧壁间隔件形成在从相对于第一侧壁间隔件选择性地移除的材料延伸到基板的第一侧壁间隔物的上方。 形成接触第二侧壁间隔物并与衬底隔开的导电区域。 第二侧壁间隔件可选择性地移除以在基板和导电区域之间形成开口。 开口填充有导电材料以将导电材料电耦合到基底。

公开(公告)号：US6130156A

公开(公告)日：2000-10-10

申请号：US281538

申请日：1999-03-30

申请人： Robert H. Havemann ,  Girish A. Dixit ,  Stephen W. Russell

发明人： Robert H. Havemann ,  Girish A. Dixit ,  Stephen W. Russell

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76843 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76886 ,  H01L2221/1089 ,  H01L23/53219 ,  H01L23/53233 ,  H01L2924/0002

摘要： A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.

摘要翻译： 一种制造互连的方法，其中最初提供第一层导电互连（3）。 形成通孔（7），其通过延伸到第一互连层的壁限定。 在导电互连和导电金属（11）的第一层之间形成一层钛（9）。 第一层导电金属形成在通孔的壁上，具有相对于特定蚀刻物质的预定蚀刻速率，并且第二层导电金属（13）形成在具有蚀刻的第一导电金属层上 相对于比第一层大的特定蚀刻物质的速率，并且优选地延伸到通孔中。 导电互连的第一层优选为铝，第一层导电金属优选为含有约1％至约100％铜的金属，其余基本上为铝，而第二层导电金属优选为 铜掺杂的铝的铜含量低于第一导电层。

公开(公告)号：US5488015A

公开(公告)日：1996-01-30

申请号：US246432

申请日：1994-05-20

申请人： Robert H. Havemann ,  Shin-Puu Jeng ,  Bruce E. Gnade ,  Chih-Chen Cho

发明人： Robert H. Havemann ,  Shin-Puu Jeng ,  Bruce E. Gnade ,  Chih-Chen Cho

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/441 ,  H01L21/469

CPC分类号： H01L21/02362 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02359 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/118

摘要： This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

摘要翻译： 本发明提供了一种半导体器件及其制造方法，其显着降低了相邻导体之间的电容，以及强调机械强度，蚀刻兼容性和良好热传递的层间电介质结构。 该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成 层间电介质，并提供机械强度，热传递和用于通孔蚀刻的固体层。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。

公开(公告)号：US5403759A

公开(公告)日：1995-04-04

申请号：US955942

申请日：1992-10-02

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L21/768 ,  H01L27/11 ,  H01L21/265

CPC分类号： H01L27/1108 ,  H01L21/76889 ,  H01L21/76895 ,  Y10S257/903

摘要： A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

摘要翻译： 一种在晶片上制造晶体管的方法，包括： 在绝缘体34的顶部上形成掺杂晶体管体42; 晶体管体中的掺杂源极/漏极区域; 在晶体管本体的顶部形成栅极氧化物44; 沿着晶体管本体形成侧壁间隔物; 在所述晶体管本体上沉积金属层; 在所述金属层上形成非晶硅层，所述非晶硅层以栅极和局部互连配置构图; 退火以在晶体管体内的源极/漏极区之上形成硅化物区域，并且其中金属层与非晶硅层反应以产生硅化栅极50和硅化局部互连50; 并且蚀刻金属层的非硅化部分以留下硅化物源极/漏极区域，硅化栅极和硅化局部互连。

公开(公告)号：US5395798A

公开(公告)日：1995-03-07

申请号：US812241

申请日：1991-12-19

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/441

CPC分类号： H01L21/28518 ,  H01L21/76838 ,  Y10S148/147

摘要： A method for forming a refractory metal silicide on a semiconductor device is disclosed. The method comprises the steps of depositing a layer of refractory metal on the device and reacting the layer with nitrogen. The reaction is accomplished at a partial pressure of nitrogen greater than one atmosphere. The disclosed process allows thin layers of low resistance silicide to be formed for use as an ohmic contact while also forming a nitride layer for use as a device-to-device interconnection.

摘要翻译： 公开了一种在半导体器件上形成难熔金属硅化物的方法。 该方法包括以下步骤：在该装置上沉积难熔金属层并使该层与氮反应。 反应在大于1个大气压的氮气分压下完成。 所公开的方法允许形成薄层的低电阻硅化物以用作欧姆接触，同时还形成用作器件到器件互连的氮化物层。

公开(公告)号：US5252502A

公开(公告)日：1993-10-12

申请号：US924209

申请日：1992-08-03

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/265 ,  H01L21/44

CPC分类号： H01L29/66757 ,  H01L29/42384

摘要： This is a method of fabricating a transistor on a wafer. The method comprises: forming an oxide layer 40 on a doped silicon layer 32; depositing a first resist over the oxide 40 and patterning the resist with a gate oxide configuration having a predetermined gate oxide length; etching to remove portions of the oxide layer 40 to expose portions of the silicon layer 32 using the resist as a mask; depositing a metal layer 42 over remaining portions of the oxide layer and exposed portions of the silicon layer; annealing the wafer to react portions of the metal layer with exposed portions of the silicon layer to form a metal silicide 44; depositing a second resist over the metal and patterning the second resist with a gate configuration having a gate length A smaller than the gate oxide length B; etching the metal to form a metal gate 42 and exposing portions of gate oxide; and implanting dopant adjacent the gate through the exposed gate oxide to provide source/drain regions 38 aligned to edges of the gate, utilizing the metal gate 42 as a mask to substantially prevent doping underneath the gate, whereby the gate need not be precisely centered on the gate oxide and thus difficulties in alignment are substantially eliminated.

摘要翻译： 这是在晶片上制造晶体管的方法。 该方法包括：在掺杂硅层32上形成氧化物层40; 在氧化物40上沉积第一抗蚀剂，并以具有预定栅极氧化物长度的栅极氧化物构型图案化抗蚀剂; 蚀刻以除去氧化物层40的部分，以使用抗蚀剂作为掩模来露出硅层32的部分; 在氧化物层的剩余部分和硅层的暴露部分上沉积金属层42; 退火晶片以使金属层的部分与硅层的暴露部分反应以形成金属硅化物44; 在所述金属上沉积第二抗蚀剂并且以栅极长度A小于所述栅极氧化物长度B的栅极配置图案化所述第二抗蚀剂; 蚀刻金属以形成金属栅极42并暴露栅极氧化物的部分; 以及通过所述暴露的栅极氧化物在所述栅极附近注入掺杂剂以提供与所述栅极的边缘对准的源极/漏极区域38，利用所述金属栅极42作为掩模，以基本上防止在所述栅极下面的掺杂，由此所述栅极不需要精确地居中在 栅极氧化物因此基本上消除了对准困难。