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    SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES
    1.
    发明申请
    SPACER-LESS TRANSISTOR INTEGRATION SCHEME FOR HIGH-K GATE DIELECTRICS AND SMALL GATE-TO-GATE SPACES APPLICABLE TO SI, SIGE AND STRAINED SILICON SCHEMES 有权
    适用于SI，信号和应变硅计划的高K栅介质和小门到门空间的间隔不足的晶体管集成方案

    公开(公告)号：US20080102583A1

    公开(公告)日：2008-05-01

    申请号：US11960554

    申请日：2007-12-19

    申请人： David Pritchard ,  Hemanshu Bhatt ,  David Price

    发明人： David Pritchard ,  Hemanshu Bhatt ,  David Price

    IPC分类号： H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/66606

    摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

    摘要翻译： 晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。 在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。 在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。 该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

    Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes
    4.
    发明申请
    Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes 审中-公开
    用于高k栅极电介质和适用于Si，SiGe应变硅方案的小栅极到栅极空间的无间隔晶体管集成方案

    公开(公告)号：US20050191812A1

    公开(公告)日：2005-09-01

    申请号：US10791337

    申请日：2004-03-01

    申请人： David Pritchard ,  Hemanshu Bhatt ,  David Price

    发明人： David Pritchard ,  Hemanshu Bhatt ,  David Price

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/66606

    摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

    摘要翻译： 晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。 在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。 在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。 该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

    Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes
    5.
    发明授权
    Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemes 有权
    用于高K栅极介质和适用于Si，SiGe和应变硅方案的小栅极到栅极空间的无间隔晶体管集成方案

    公开(公告)号：US07955919B2

    公开(公告)日：2011-06-07

    申请号：US11960554

    申请日：2007-12-19

    申请人： David Pritchard ,  Hemanshu Bhatt ,  David T. Price

    发明人： David Pritchard ,  Hemanshu Bhatt ,  David T. Price

    IPC分类号： H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/4958 ,  H01L29/665 ,  H01L29/66606

    摘要： A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

    摘要翻译： 晶体管积分过程提供了用于形成栅极电极和栅极电介质层的镶嵌方法。 在栅电极形成之前沉积层间绝缘膜，以避免由相邻栅极呈现的苛刻的间隙填充要求。 在层间电介质膜中形成沟槽，随后在沟槽中沉积栅极材料。 该过程避免了由高热循环引起的对高k栅极电介质层的损坏的可能性，并且还减少或消除填充相邻栅极之间的间隙的电介质层中空隙的有问题的形成。

    Local interconnect manufacturing process
    6.
    发明申请
    Local interconnect manufacturing process 有权
    本地互连制造工艺

    公开(公告)号：US20060088990A1

    公开(公告)日：2006-04-27

    申请号：US10971961

    申请日：2004-10-22

    申请人： Santosh Menon ,  Hemanshu Bhatt ,  David Pritchard

    发明人： Santosh Menon ,  Hemanshu Bhatt ,  David Pritchard

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76895

    摘要： The present invention is directed to a method of fabricating a local interconnect. A disclosed method involves forming two separate cavities in the ILD above two electrical contacts of a transistor. A first cavity extend down to an underlying etch stop layer. The first cavity is then filled with a protective layer. The second cavity is then formed adjacent to the first cavity and extends down to expose the underlying etch stop layer. The protective layer is removed to form an expanded cavity including the first and second cavities which expose the underlying etch stop layer in the expanded cavity. The etch stop material in the expanded cavity is also removed to expose an underlying gate contact and expose one of a source or drain contact. The gate contact is then electrically connected with one of the exposed source or drain contacts to form a local interconnect.

    摘要翻译： 本发明涉及一种制造局部​​互连的方法。 所公开的方法包括在晶体管的两个电触点之上的ILD中形成两个分离的空腔。 第一腔向下延伸到下面的蚀刻停止层。 然后用保护层填充第一个空腔。 然后，第二腔形成在第一腔附近并向下延伸以露出下面的蚀刻停止层。 去除保护层以形成包括第一和第二空腔的扩展空腔，其暴露扩展空腔中的下面的蚀刻停止层。 扩散腔中的蚀刻停止材料也被去除以暴露下面的栅极接触并暴露源极或漏极接触中的一个。 然后将栅极触点与暴露的源极或漏极触点中的一个电连接以形成局部互连。

    ANALYTE MANIPULATION AND DETECTION
    9.
    发明申请
    ANALYTE MANIPULATION AND DETECTION 审中-公开
    分析操作和检测

    公开(公告)号：US20100233675A1

    公开(公告)日：2010-09-16

    申请号：US12438003

    申请日：2007-08-17

    申请人： Denise Barrault ,  Stuart Polwart ,  David Thomson ,  David Pritchard ,  Erling Sundrehagen

    发明人： Denise Barrault ,  Stuart Polwart ,  David Thomson ,  David Pritchard ,  Erling Sundrehagen

    IPC分类号： C12Q1/70 ,  C07H21/04 ,  C07K1/14 ,  C12Q1/68 ,  C07H21/02 ,  C12M1/34

    CPC分类号： G01N33/54313 ,  B01L3/502761 ,  B01L2200/0647 ,  B01L2300/0864 ,  B01L2400/0487 ,  G01N33/54326 ,  G01N33/54333 ,  G01N33/56988 ,  G01N33/56994

    摘要： Provided is a method for separating two or more analytes in a fluid, which method comprises: (a) binding each different analyte to a different functional particle in one or more binding zones, to produce two or more bound analytes; (b) allowing the bound analytes to move through a separating conduit to two or more separate functional zones; wherein, each different functional particle has, or can be controlled to have, a different function in the fluid as compared with the other functional particles; and wherein the separating conduit separates into two or more functional conduits, such that the separating conduit serves to separate the bound analytes into the separate functional conduits by means of the different functions of the different functional particles. Also provided is an apparatus for separating two or more analytes in a fluid, which apparatus comprises: (a) a binding zone; (b) two or more functional conduits; (c) a separating conduit connecting the binding zone to the two or more functional conduits; (d) a transporter for transporting the analyte through the separating conduit from the binding zone to the two or more functional conduits; and (e) optionally one or more concentrating zones in connection with at least one of the functional conduits.

    摘要翻译： 提供了一种用于分离流体中的两种或更多种分析物的方法，该方法包括：（a）将每种不同的分析物结合到一个或多个结合区域中的不同功能颗粒，以产生两种或更多种结合的分析物; （b）允许结合的分析物通过分离导管移动到两个或更多个分离的功能区; 其中，与其他功能性颗粒相比，每种不同的功能性颗粒具有或可以控制在流体中具有不同的功能; 并且其中所述分离管道分离成两个或更多个功能导管，使得所述分离管道用于通过所述不同功能颗粒的不同功能将结合的分析物分离成分离的功能导管。 还提供了一种用于在流体中分离两种或更多种分析物的装置，该装置包括：（a）结合区; （b）两个或多个功能导管; （c）将结合区域连接到两个或更多个功能导管的分离导管; （d）用于将分析物通过分离导管从结合区输送到两个或更多个功能导管的运送器; 和（e）可选地与至少一个功能导管连接的一个或多个浓缩区。

    MAGNETIC RECOGNITION SYSTEM
    10.
    发明申请
    MAGNETIC RECOGNITION SYSTEM 审中-公开
    磁识别系统

    公开(公告)号：US20100159442A1

    公开(公告)日：2010-06-24

    申请号：US12513348

    申请日：2007-11-02

    申请人： Prabhjyot Dehal ,  David Pritchard ,  Claire Geekie

    发明人： Prabhjyot Dehal ,  David Pritchard ,  Claire Geekie

    IPC分类号： C12Q1/70 ,  C07K14/00 ,  C07K16/00 ,  C12Q1/68 ,  G01N33/553

    CPC分类号： G01N33/5434 ,  G01N2446/80

    摘要： Provided is a label for an analyte, which label is attached to a magnetic or magnetizable substance, the label comprising: (a) a recognition moiety for attaching the label to the analyte; and (b) a moiety for binding or encapsulating the magnetic or magnetizable substance; wherein the moiety for binding or encapsulating the magnetic or magnetizable substance comprises a metal-binding protein, polypeptide, or peptide.

    摘要翻译： 提供了用于分析物的标签，其标签附着于磁性或可磁化物质，标签包括：（a）用于将标签附着到分析物的识别部分; 和（b）用于结合或包封磁性或可磁化物质的部分; 其中用于结合或包封磁性或可磁化物质的部分包括金属结合蛋白，多肽或肽。