公开(公告)号：US20230197817A1

公开(公告)日：2023-06-22

申请号：US17558231

申请日：2021-12-21

申请人： Debaleena NANDI ,  Cory BOMBERGER ,  Diane LANCASTER ,  Gilbert DEWEY ,  Sandeep K. PATIL ,  Mauro J. KOBRINSKY ,  Anand S. MURTHY ,  Tahir GHANI

发明人： Debaleena NANDI ,  Cory BOMBERGER ,  Diane LANCASTER ,  Gilbert DEWEY ,  Sandeep K. PATIL ,  Mauro J. KOBRINSKY ,  Anand S. MURTHY ,  Tahir GHANI

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/45 ,  H01L29/161

CPC分类号： H01L29/42392 ,  H01L29/78696 ,  H01L29/0673 ,  H01L29/458 ,  H01L29/161

摘要： Gate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) titanium silicide conductive contact material on the second pEPI region.

公开(公告)号：US20230207651A1

公开(公告)日：2023-06-29

申请号：US17561686

申请日：2021-12-23

申请人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Tahir GHANI ,  Tricia MEYER ,  Cory BOMBERGER ,  Glenn A. GLASS ,  Stephen M. CEA ,  Anant H. JAHAGIRDAR

发明人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Tahir GHANI ,  Tricia MEYER ,  Cory BOMBERGER ,  Glenn A. GLASS ,  Stephen M. CEA ,  Anant H. JAHAGIRDAR

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06

CPC分类号： H01L29/42392 ,  H01L29/78696 ,  H01L29/0673

摘要： Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has an upper portion and a lower epitaxial extension portion.

公开(公告)号：US20230207551A1

公开(公告)日：2023-06-29

申请号：US17561693

申请日：2021-12-23

申请人： Sukru YEMENICIOGLU ,  Richard E. SCHENKER ,  Xinning WANG ,  Mauro J. KOBRINSKY ,  Tahir GHANI

发明人： Sukru YEMENICIOGLU ,  Richard E. SCHENKER ,  Xinning WANG ,  Mauro J. KOBRINSKY ,  Tahir GHANI

IPC分类号： H01L27/02 ,  H01L23/522 ,  G06F30/394

CPC分类号： H01L27/0207 ,  H01L23/5226 ,  G06F30/394

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to standard cell architectures without power delivery space allocation. Other embodiments may be described or claimed.

公开(公告)号：US20230207696A1

公开(公告)日：2023-06-29

申请号：US17561518

申请日：2021-12-23

申请人： Mohammad HASAN ,  Wonil CHUNG ,  Biswajeet GUHA ,  Saptarshi MANDAL ,  Pratik PATEL ,  Tahir GHANI ,  Stephen M. CEA ,  Anand S. MURTHY

发明人： Mohammad HASAN ,  Wonil CHUNG ,  Biswajeet GUHA ,  Saptarshi MANDAL ,  Pratik PATEL ,  Tahir GHANI ,  Stephen M. CEA ,  Anand S. MURTHY

IPC分类号： H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7843 ,  H01L29/785 ,  H01L29/42392

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.

公开(公告)号：US20230197838A1

公开(公告)日：2023-06-22

申请号：US17558046

申请日：2021-12-21

申请人： Mohammad HASAN ,  Leonard P. GULER ,  Anand S. Murthy ,  Pratik PATEL ,  Tahir GHANI

发明人： Mohammad HASAN ,  Leonard P. GULER ,  Anand S. Murthy ,  Pratik PATEL ,  Tahir GHANI

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

摘要： Gate-all-around integrated circuit structures having source or drain-last structures, and methods of fabricating gate-all-around integrated circuit structures having source or drain-last structures, are described. For example, a method of fabricating an integrated circuit structure includes forming a vertical arrangement of nanowires. A permanent gate stack is then formed over the vertical arrangements of nanowires. The permanent gate stack includes a high-k gate dielectric layer and a metal gate electrode. Subsequent to forming the permanent gate stack, a first epitaxial source or drain structure is formed at a first end of the vertical arrangement of nanowires, and a second epitaxial source or drain structure is formed at a second end of the vertical arrangement of nanowires.

公开(公告)号：US20230197816A1

公开(公告)日：2023-06-22

申请号：US17558061

申请日：2021-12-21

申请人： Mohammad HASAN ,  Mohit K. HARAN ,  Tahir GHANI ,  Anand S. MURTHY ,  Rushabh SHAH

发明人： Mohammad HASAN ,  Mohit K. HARAN ,  Tahir GHANI ,  Anand S. MURTHY ,  Rushabh SHAH

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/78696

摘要： Integrated circuit structures having metal gate plug landed on dielectric anchor, and methods of fabricating integrated circuit structures having metal gate plug landed on dielectric anchor, are described. For example, an integrated circuit structure includes a sub-fin in a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is surrounding the horizontally stacked nanowires. A gate electrode structure is over the gate dielectric material layer. A dielectric structure is laterally spaced apart from the plurality of horizontally stacked nanowires, the dielectric structure having a bottommost surface below an uppermost surface of the STI structure. A dielectric gate plug is on the dielectric structure.

公开(公告)号：US20170133277A1

公开(公告)日：2017-05-11

申请号：US15411095

申请日：2017-01-20

申请人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Annalisa CAPPELLANI ,  Stephen M. CEA ,  Rafael RIOS ,  Glenn A. GLASS

发明人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Annalisa CAPPELLANI ,  Stephen M. CEA ,  Rafael RIOS ,  Glenn A. GLASS

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L27/12 ,  H01L29/06 ,  H01L27/092 ,  H01L21/84

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

公开(公告)号：US20230197855A1

公开(公告)日：2023-06-22

申请号：US17557995

申请日：2021-12-21

申请人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Leonard P. GULER ,  Tahir GHANI

发明人： Mohammad HASAN ,  Nitesh KUMAR ,  Rushabh SHAH ,  Anand S. MURTHY ,  Pratik PATEL ,  Leonard P. GULER ,  Tahir GHANI

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC分类号： H01L29/78618 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.

公开(公告)号：US20160240616A1

公开(公告)日：2016-08-18

申请号：US15024348

申请日：2013-12-16

申请人： Stephen M. CEA ,  Roza KOTLYAR ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Kelin J. KUHN ,  Tahir GHANI

发明人： Stephen M. CEA ,  Roza KOTLYAR ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Kelin J. KUHN ,  Tahir GHANI

IPC分类号： H01L29/10 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/092 ,  H01L29/04 ,  H01L29/161

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66818 ,  H01L29/7781 ,  H01L29/7782

摘要： Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor.

摘要翻译： 与没有松弛衬底的应变NMOS和PMOS器件有关的技术和方法，以及这样的半导体器件的系统及其方法。

公开(公告)号：US20200098887A1

公开(公告)日：2020-03-26

申请号：US16143326

申请日：2018-09-26

申请人： Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Sean MA ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Tahir GHANI ,  Justin WEBER ,  Shriram SHIVARAMAN

发明人： Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Jack T. KAVALIEROS ,  Sean MA ,  Seung Hoon SUNG ,  Nazila HARATIPOUR ,  Tahir GHANI ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC分类号： H01L29/51 ,  H01L29/786 ,  H01L29/49 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66

摘要： Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.