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    Continuously scalable width and height semiconductor fins
    1.
    发明授权
    Continuously scalable width and height semiconductor fins 有权
    连续可调的宽度和高度半导体鳍片

    公开(公告)号：US08927432B2

    公开(公告)日：2015-01-06

    申请号：US13523048

    申请日：2012-06-14

    申请人： Dechao Guo ,  Yang Liu ,  Chengwen Pei ,  Yue Tan

    发明人： Dechao Guo ,  Yang Liu ,  Chengwen Pei ,  Yue Tan

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L27/1211 ,  H01L21/845

    摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

    摘要翻译： 通过为鳍式场效应晶体管所采用的半导体鳍片的物理尺寸提供两个独立的变量，可以为鳍式场效应晶体管提供任意和连续的可变电流。 在掩埋绝缘体层上的半导体层上形成凹陷区域。 在半导体层上形成电介质盖层。 在电介质盖层上形成一次性心轴结构，并且围绕一次性心轴结构形成间隔结构。 在掩蔽离子注入期间，选择的间隔结构可以在结构上受损。 使用蚀刻以比未损坏的间隔物结构更大的蚀刻速率去除结构损坏的间隔物结构。 在去除一次性心轴结构之后，将半导体层图案化成具有不同高度和/或不同宽度的多个半导体翅片。 随后可以形成具有不同宽度和/或高度的鳍场效应晶体管。

    CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS
    2.
    发明申请
    CONTINUOUSLY SCALABLE WIDTH AND HEIGHT SEMICONDUCTOR FINS 有权

    公开(公告)号：US20130334602A1

    公开(公告)日：2013-12-19

    申请号：US13523048

    申请日：2012-06-14

    申请人： Dechao Guo ,  Yang Liu ,  Chengwen Pei ,  Yue Tan

    发明人： Dechao Guo ,  Yang Liu ,  Chengwen Pei ,  Yue Tan

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L27/1211 ,  H01L21/845

    摘要： Arbitrarily and continuously scalable on-currents can be provided for fin field effect transistors by providing two independent variables for physical dimensions for semiconductor fins that are employed for the fin field effect transistors. A recessed region is formed on a semiconductor layer over a buried insulator layer. A dielectric cap layer is formed over the semiconductor layer. Disposable mandrel structures are formed over the dielectric cap layer and spacer structures are formed around the disposable mandrel structures. Selected spacer structures can be structurally damaged during a masked ion implantation. An etch is employed to remove structurally damaged spacer structures at a greater etch rate than undamaged spacer structures. After removal of the disposable mandrel structures, the semiconductor layer is patterned into a plurality of semiconductor fins having different heights and/or different width. Fin field effect transistors having different widths and/or heights can be subsequently formed.

    Epitaxial extension CMOS transistor
    5.
    发明授权
    Epitaxial extension CMOS transistor 有权
    外延扩展CMOS晶体管

    公开(公告)号：US09076817B2

    公开(公告)日：2015-07-07

    申请号：US13198152

    申请日：2011-08-04

    申请人： Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    发明人： Chengwen Pei ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L29/66 ,  H01L29/51

    CPC分类号： H01L29/6656 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

    摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

    摘要翻译： 通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一 并且通过形成大于第一深度的第二深度的一对第二沟槽。 去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。 可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。 或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

    Self-aligned devices and methods of manufacture
    6.
    发明授权
    Self-aligned devices and methods of manufacture 失效
    自对准装置和制造方法

    公开(公告)号：US08691697B2

    公开(公告)日：2014-04-08

    申请号：US12943956

    申请日：2010-11-11

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L21/302 ,  B44C1/22

    CPC分类号： H01L21/31056 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method includes forming patterned lines on a substrate having a predetermined pitch. The method further includes forming spacer sidewalls on sidewalls of the patterned lines. The method further includes forming material in a space between the spacer sidewalls of adjacent patterned lines. The method further includes forming another patterned line from the material by protecting the material in the space between the spacer sidewalls of adjacent patterned lines while removing the spacer sidewalls. The method further includes transferring a pattern of the patterned lines and the another patterned line to the substrate.

    摘要翻译： 一种方法包括在具有预定间距的基底上形成图案线。 该方法还包括在图案化线的侧壁上形成间隔壁。 该方法还包括在相邻图案线的间隔壁侧壁之间的空间中形成材料。 该方法还包括通过在相邻图案化线的间隔壁侧壁之间的空间中保护材料同时去除间隔壁侧壁而从该材料形成另一图案化线。 该方法还包括将图案化线和另一图案化线的图案转移到衬底。

    Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate
    8.
    发明授权
    Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate 有权
    在非常薄的半导体绝缘体（ETSOI）衬底上形成的嵌入式动态随机存取存储器件

    公开(公告)号：US08575670B2

    公开(公告)日：2013-11-05

    申请号：US13316056

    申请日：2011-12-09

    申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/945

    摘要： A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.

    摘要翻译： 一种存储器件，包括具有厚度小于30nm的掩埋介电层的SOI衬底，以及穿过SOI层的延伸沟槽和埋入电介质层到SOI衬底的基底半导体层中的沟槽。 电容器存在于沟槽的下部。 电介质垫片存在于沟槽上部的侧壁上。 介质间隔物存在于沟槽的部分，其中侧壁由SOI层和埋入的介电层提供。 导电材料填充物存在于沟槽的上部。 半导体器件存在于与沟槽相邻的SOI层上。 半导体器件通过导电材料填充与电容器电连通。

    Structure and method to form nanopore
    10.
    发明授权
    Structure and method to form nanopore 有权
    结构和方法形成纳米孔

    公开(公告)号：US08535544B2

    公开(公告)日：2013-09-17

    申请号：US12843228

    申请日：2010-07-26

    申请人： Chengwen Pei ,  Zhengwen Li

    发明人： Chengwen Pei ,  Zhengwen Li

    IPC分类号： B44C1/22 ,  B82Y40/00

    CPC分类号： G01N33/48721 ,  B32B3/266 ,  B81B2201/058 ,  B81B2203/0384 ,  B81C1/00087 ,  C30B33/10 ,  Y10T428/249975

    摘要： A method of fabricating a material having nanoscale pores is provided. In one embodiment, the method of fabricating a material having nanoscale pores may include providing a single crystal semiconductor. The single crystal semiconductor layer is then patterned to provide an array of exposed portions of the single crystal semiconductor layer having a width that is equal to the minimum lithographic dimension. The array of exposed portion of the single crystal semiconductor layer is then etched using an etch chemistry having a selectivity for a first crystal plane to a second crystal plane of 100% or greater. The etch process forms single or an array of trapezoid shaped pores, each of the trapezoid shaped pores having a base that with a second width that is less than the minimum lithographic dimension.

    摘要翻译： 提供了制造具有纳米尺度孔的材料的方法。 在一个实施例中，制造具有纳米尺度孔的材料的方法可以包括提供单晶半导体。 然后对单晶半导体层进行构图以提供具有等于最小光刻尺寸的宽度的单晶半导体层的暴露部分的阵列。 然后使用具有对第一晶面的选择性至100％或更大的第二晶体面的蚀刻化学品蚀刻单晶半导体层的暴露部分的阵列。 蚀刻工艺形成单个或一组梯形形孔，每个梯形孔具有基部，其具有小于最小光刻尺寸的第二宽度。