公开(公告)号：US08890329B2

公开(公告)日：2014-11-18

申请号：US13455539

申请日：2012-04-25

申请人： Do Hyung Kim ,  Dae Byoung Kang ,  Seung Chul Han

发明人： Do Hyung Kim ,  Dae Byoung Kang ,  Seung Chul Han

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/538 ,  H01L27/146 ,  H01L21/50 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad.

摘要翻译： 提供一种完全具有小高度的半导体器件，其对输入/输出信号执行扇出操作并形成短路径。 半导体器件包括具有第一表面的第一半导体管芯，与第一表面相对的第二表面，将第一和第二表面彼此连接的第三表面，设置在第一表面上的第一接合焊盘，以及第一通孔 在第一表面和第二表面之间通过并电连接到第一接合焊盘。 第一再分配部分设置在第二表面下方，并且包括电连接到第一贯通电极的第一再分配层。 第二再分配部分设置在第一表面上并且包括电连接到第一接合焊盘的第二再分配层。

公开(公告)号：US20120273946A1

公开(公告)日：2012-11-01

申请号：US13455539

申请日：2012-04-25

申请人： Do Hyung Kim ,  Dae Byoung Kang ,  Seung Chul Han

发明人： Do Hyung Kim ,  Dae Byoung Kang ,  Seung Chul Han

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad.

摘要翻译： 提供一种完全具有小高度的半导体器件，其对输入/输出信号执行扇出操作并形成短路径。 半导体器件包括具有第一表面的第一半导体管芯，与第一表面相对的第二表面，将第一和第二表面彼此连接的第三表面，设置在第一表面上的第一接合焊盘，以及第一通孔 在第一表面和第二表面之间通过并电连接到第一接合焊盘。 第一再分配部分设置在第二表面下方，并且包括电连接到第一贯通电极的第一再分配层。 第二再分配部分设置在第一表面上并且包括电连接到第一接合焊盘的第二再分配层。

公开(公告)号：US07982298B1

公开(公告)日：2011-07-19

申请号：US12327763

申请日：2008-12-03

申请人： Dae Byoung Kang ,  Sung Jin Yang ,  Jung Tae Ok ,  Jae Dong Kim

发明人： Dae Byoung Kang ,  Sung Jin Yang ,  Jung Tae Ok ,  Jae Dong Kim

IPC分类号： H01L23/48

CPC分类号： H01L25/03 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552

摘要： In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack. In other embodiments of the present invention, a semiconductor die which is electrically connected to the conductive pattern of the substrate is encapsulated with an inner package body which itself is formed to include through-mold vias used to facilitate the electrical connection thereof to another semiconductor die stacked thereon. In each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.

摘要翻译： 根据本发明，提供了包装封装半导体器件的多个实施例，其包括缩短的电信号路径以优化电性能。 在每个实施例中，半导体器件包括其上形成有导电图案的衬底。 在某些实施例中，半导体封装和一个或多个半导体管芯垂直堆叠在衬底上，并与其导电图案电连通。 一个或多个半导体管芯可以包括形成在其中的穿硅通孔，以便于其与衬底的导电图案或垂直堆叠内的其他电子部件的电连接。 类似地，半导体封装可以设置有通孔通孔，以便于其与垂直堆叠内的其它电子部件的电连接。 在本发明的其他实施例中，电连接到衬底的导电图案的半导体管芯被封装成内部封装本体，内部封装本体形成为包括用于促进其与另一半导体管芯的电连接的通孔通孔 堆叠在其上。 在半导体器件的每个实施例中，其垂直堆叠的电子部件可以被也部分地覆盖衬底的封装体覆盖。

公开(公告)号：US08089145B1

公开(公告)日：2012-01-03

申请号：US12272606

申请日：2008-11-17

申请人： Gwang Ho Kim ,  Jin Seong Kim ,  Dong Joo Park ,  Dae Byoung Kang

发明人： Gwang Ho Kim ,  Jin Seong Kim ,  Dong Joo Park ,  Dae Byoung Kang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/02 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L23/49541 ,  H01L21/4842 ,  H01L23/3107 ,  H01L23/49517 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

摘要： In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads are provided in two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body.

摘要翻译： 根据本发明，提供了包括唯一配置的引线框的半导体封装（例如，QFP封装），其尺寸和配置为使半导体封装中的暴露引线的可用数量最大化。 更具体地，本发明的半导体封装包括限定多个周边边缘段的大致平面的管芯焊盘或管芯焊盘。 此外，半导体封装包括多个引线。 这些引线中的一些以两个同心的行或环提供，其至少部分地绕过管芯焊盘，其他引线包括从半导体封装的封装主体的相应侧表面突出的部分。 连接到管芯焊盘的顶表面的是至少一个半导体管芯，其电连接到至少一些引线。 芯片焊盘，引线和半导体管芯的至少一部分被封装体封装。

公开(公告)号：US08441123B1

公开(公告)日：2013-05-14

申请号：US12540593

申请日：2009-08-13

申请人： Dong Hee Lee ,  Min Yoo ,  Dae Byoung Kang ,  Bae Yong Kim

发明人： Dong Hee Lee ,  Min Yoo ,  Dae Byoung Kang ,  Bae Yong Kim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/131 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/014

摘要： A semiconductor device has a first semiconductor die having at least one metal pillar formed along an inner perimeter and at least one bond pad formed along an outer perimeter. A second semiconductor die has at least one metal pillar. A conductive bump connects the at least one metal pillar of the first semiconductor die to the at least one metal pillar of the second semiconductor die. At least one metal dam is formed on the first semiconductor die between the at least one metal pillar of the first semiconductor die and the at least one bond pad.

摘要翻译： 半导体器件具有第一半导体管芯，该第一半导体管芯具有沿着内周边形成的至少一个金属柱和沿外周形成的至少一个接合焊盘。 第二半导体管芯具有至少一个金属柱。 导电凸块将第一半导体管芯的至少一个金属柱连接到第二半导体管芯的至少一个金属柱。 在第一半导体管芯上的至少一个金属柱与第一半导体管芯的至少一个接合焊盘之间形成至少一个金属坝。

公开(公告)号：US06897550B1

公开(公告)日：2005-05-24

申请号：US10459097

申请日：2003-06-11

申请人： Curtis M. Zwenger ,  Raul M. Guerrero ,  Dae Byoung Kang ,  Chul Woo Park

发明人： Curtis M. Zwenger ,  Raul M. Guerrero ,  Dae Byoung Kang ,  Chul Woo Park

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory card comprising a leadframe having at least one die pad, a plurality of contacts, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. The traces are bent in a manner wherein the die pad and the contacts extend along respective ones of spaced, generally parallel frame planes. Disposed on and extending from the die pad and the traces is a plurality of stand-offs. At least one semiconductor die is attached to the die pad and electrically connected to at least one of the traces. A body at least partially encapsulates the leadframe and the semiconductor die such that the contacts are exposed in a bottom surface defined by the body.

摘要翻译： 一种存储卡，包括具有至少一个管芯焊盘，多个触点和从相应的触头朝向芯片焊盘延伸的多个导电迹线的引线框架。 轨迹以这样的方式弯曲，其中，芯片焊盘和触头沿相应的间隔开的大致平行的框架平面延伸。 放置在芯片焊盘上并从芯片焊盘延伸出来的迹线是多个对立的。 至少一个半导体管芯附接到管芯焊盘并电连接到至少一个迹线。 主体至少部分地封装引线框架和半导体管芯，使得触点暴露在由主体限定的底部表面中。