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    Process for the formation of dielectric isolation structures in semiconductor devices
    1.
    发明申请
    Process for the formation of dielectric isolation structures in semiconductor devices 审中-公开
    在半导体器件中形成绝缘隔离结构的工艺

    公开(公告)号：US20050009294A1

    公开(公告)日：2005-01-13

    申请号：US10853565

    申请日：2004-05-25

    申请人： Donata Piccolo ,  Lorena Beghin ,  Marcello Mariani ,  Chiara Savardi

    发明人： Donata Piccolo ,  Lorena Beghin ,  Marcello Mariani ,  Chiara Savardi

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76229 ,  H01L21/76232

    摘要： A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material.

    摘要翻译： 在硅衬底上形成电介质隔离结构的工艺包括在衬底中形成至少一个沟槽，在氧化环境中进行高温处理，以在沟槽的壁和底部形成二氧化硅的第一衬里层 ，并且进行二氧化硅沉积处理以在第一衬里层上形成第二衬里层。 还进行氮化硅沉积处理以在第二衬里层上形成第三衬里层。 沟槽填充有隔离材料。

    PROCESS FOR THE FORMATION OF DIELECTRIC ISOLATION STRUCTURES IN SEMICONDUCTOR DEVICES
    2.
    发明申请
    PROCESS FOR THE FORMATION OF DIELECTRIC ISOLATION STRUCTURES IN SEMICONDUCTOR DEVICES 审中-公开
    在半导体器件中形成介电隔离结构的方法

    公开(公告)号：US20080213970A1

    公开(公告)日：2008-09-04

    申请号：US12014883

    申请日：2008-01-16

    申请人： Donata PICCOLO ,  Lorena Katia Beghin ,  Marcello Mariani ,  Chiara Savardi

    发明人： Donata PICCOLO ,  Lorena Katia Beghin ,  Marcello Mariani ,  Chiara Savardi

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/76232

    摘要： A process for forming a dielectric isolation structure on a silicon substrate includes forming at least one trench in the substrate, performing a high-temperature treatment in an oxidizing environment to form a first liner layer of silicon dioxide on the walls and the bottom of the trench, and performing a silicon dioxide deposition treatment to form a second liner layer on the first liner layer. A silicon nitride deposition treatment is also performed to form a third liner layer on the second liner layer. The trench is filled with isolating material.

    摘要翻译： 在硅衬底上形成电介质隔离结构的工艺包括在衬底中形成至少一个沟槽，在氧化环境中进行高温处理，以在沟槽的壁和底部形成二氧化硅的第一衬里层 ，并且进行二氧化硅沉积处理以在第一衬里层上形成第二衬里层。 还进行氮化硅沉积处理以在第二衬里层上形成第三衬里层。 沟槽填充有隔离材料。

    Method for manufacturing semiconductor integrated circuit structures
    3.
    发明授权
    Method for manufacturing semiconductor integrated circuit structures 有权
    半导体集成电路结构的制造方法

    公开(公告)号：US07163898B2

    公开(公告)日：2007-01-16

    申请号：US10631463

    申请日：2003-07-30

    申请人： Marcello Mariani ,  Lorena Beghin

    发明人： Marcello Mariani ,  Lorena Beghin

    IPC分类号： H01L21/302

    CPC分类号： H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method for manufacturing circuit structures integrated in a semiconductor substrate that includes regions, in particular isolation regions, includes the steps of:—depositing a conductive layer to be patterned onto the semiconductor substrate;—forming a first mask of a first material on the conductive layer;—forming a second mask made of a second material that is different from the first and provided with first openings of a first size having spacers formed on their sidewalls to uncover portions of the first mask having a second width which is smaller than the first;—partly etching away the conductive layer through the first and second masks such to leave grooves of the second width;—removing the second mask and the spacers; and—etching the grooves through the first mask to uncover the regions provided in the substrate and form conductive lines.

    摘要翻译： 一种用于制造集成在包括特别是隔离区域的区域的半导体衬底中的电路结构的方法包括以下步骤： - 将待图案化的导电层沉积到半导体衬底上; - 在导电上形成第一材料的第一掩模 形成由与第一材料不同的第二材料制成的第二掩模，第二掩模具有第一尺寸的第一开口，其具有形成在其侧壁上的间隔物，以露出第一掩模的部分，其具有小于第一宽度的第一宽度 ; - 通过所述第一和第二掩模去除所述导电层，以留下所述第二宽度的凹槽; - 移除所述第二掩模和所述间隔物; 并且通过第一掩模蚀刻凹槽以露出设置在基板中的区域并形成导电线。

    Shallow trench isolation for a memory
    4.
    发明授权
    Shallow trench isolation for a memory 有权
    浅沟槽隔离用于记忆

    公开(公告)号：US08664702B2

    公开(公告)日：2014-03-04

    申请号：US13315337

    申请日：2011-12-09

    申请人： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    发明人： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    IPC分类号： H01L29/76

    CPC分类号： H01L29/788 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    摘要： In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

    摘要翻译： 在一些实施例中，具有在其侧面上的间隔物的栅极结构可以用作掩模以在诸如闪存的微电子存储器中形成自对准沟槽。 在一些实施例中，门结构的第一部分可以与侧壁间隔件一起用于形成掩模。 然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

    Shallow trench isolation for a memory
    8.
    发明授权
    Shallow trench isolation for a memory 有权
    浅沟槽隔离用于记忆

    公开(公告)号：US08097506B2

    公开(公告)日：2012-01-17

    申请号：US12341002

    申请日：2008-12-22

    申请人： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    发明人： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/302

    CPC分类号： H01L29/788 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    摘要： In some embodiments, a gate structure with a spacer on its side may be used as a mask to form self-aligned trenches in a microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

    摘要翻译： 在一些实施例中，具有在其侧面上的间隔物的栅极结构可以用作掩模以在诸如闪存的微电子存储器中形成自对准沟槽。 在一些实施例中，门结构的第一部分可以与侧壁间隔件一起用于形成掩模。 然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

    Forming Three Dimensional Isolation Structures
    9.
    发明申请
    Forming Three Dimensional Isolation Structures 有权
    形成三维隔离结构

    公开(公告)号：US20120126374A1

    公开(公告)日：2012-05-24

    申请号：US12952240

    申请日：2010-11-23

    申请人： Enzo Carollo ,  Marcello Mariani ,  Sara Marelli ,  Luca Di Piazza

    发明人： Enzo Carollo ,  Marcello Mariani ,  Sara Marelli ,  Luca Di Piazza

    IPC分类号： H01L29/66 ,  H01L21/31

    CPC分类号： H01L29/0649 ,  H01L21/76224

    摘要： A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.

    摘要翻译： 包括在两个垂直方向上延伸的并联沟槽组的三维浅沟槽隔离结构可以通过在第一组平行沟槽中沉积共形沉积而形成，氧化第二组沟槽以使得能够选择性地沉积在所述第二组沟槽中， 然后共形地沉积在所述第二组沟槽中。 在一些实施例中，可以仅使用一个湿法退火，一次回蚀和一个高密度等离子体化学气相沉积步骤来填充两组沟槽。