Magnetoresistive stack/structure and methods therefor

    公开(公告)号:US12167702B2

    公开(公告)日:2024-12-10

    申请号:US18123729

    申请日:2023-03-20

    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.

    Preprogrammed data recovery
    5.
    发明授权

    公开(公告)号:US10659081B2

    公开(公告)日:2020-05-19

    申请号:US15846242

    申请日:2017-12-19

    Abstract: Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ECC correction. Embodiments include storage of multiple copies of the data where ECC correction is performed before and after majority voting with respect to the multiple copies. Multiple levels of ECC correction can also be performed where one level of ECC is performed at the local level (e.g. on-chip), whereas another level of ECC correction is performed at a system level.

    PREPROGRAMMED DATA RECOVERY
    9.
    发明申请

    公开(公告)号:US20180205396A1

    公开(公告)日:2018-07-19

    申请号:US15846242

    申请日:2017-12-19

    Abstract: Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ECC correction. Embodiments include storage of multiple copies of the data where ECC correction is performed before and after majority voting with respect to the multiple copies. Multiple levels of ECC correction can also be performed where one level of ECC is performed at the local level (e.g. on-chip), whereas another level of ECC correction is performed at a system level.

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