公开(公告)号：US06255221B1

公开(公告)日：2001-07-03

申请号：US09215020

申请日：1998-12-17

申请人： Eric A. Hudson ,  Jaroslaw W. Winniczek ,  Joel M. Cook ,  Helen L. Maynard

发明人： Eric A. Hudson ,  Jaroslaw W. Winniczek ,  Joel M. Cook ,  Helen L. Maynard

IPC分类号： H01L2102

CPC分类号： H01L21/31116 ,  Y10S438/91

摘要： Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source. The pulsed application of the TCP power source is configured to etch through the dielectric layer to at least one contact via hole or open area while substantially reducing damage to the transistor gate oxides of the transistor devices.

摘要翻译： 公开了用于在高密度等离子体蚀刻器中蚀刻电介质层的方法和系统。 一种方法包括在电介质层上提供具有光致抗蚀剂掩模的晶片，以便限定至少一个电连接到晶片的硅衬底的接触通孔或开放区域。 然后，该方法进行将晶片插入高密度等离子体蚀刻器中，并脉冲施加高密度等离子体蚀刻器的TCP电源。 脉冲应用包括确定期望的蚀刻性能特性，其包括与TCP源的连续波应用相关联的光致抗蚀剂选择性和蚀刻速率。 然后，选择TCP源的脉冲应用的占空比，并且缩放TCP源的脉冲应用的峰值功率，以便匹配由TCP源的连续波应用传递的周期平均功率。 TCP电源的脉冲施加被配置为通过介电层蚀刻到至少一个接触通孔或开放区域，同时基本上减少对晶体管器件的晶体管栅极氧化物的损害。

公开(公告)号：US20080153291A1

公开(公告)日：2008-06-26

申请号：US12044537

申请日：2008-03-07

申请人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

发明人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

IPC分类号： H01L21/44 ,  C23C16/00

CPC分类号： C23C18/1612 ,  C23C18/14 ,  C23C18/161 ,  C23C18/1619 ,  C23C18/1651 ,  C23C18/1667 ,  C23C18/168 ,  C23C18/31 ,  H01L21/288

摘要： Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

摘要翻译： 概括地说，提供了一种在半导体晶片（“晶片”）上沉积材料的方法和装置。 更具体地，该方法和装置提供了暴露于化学镀溶液的晶片的表面的选择性加热。 通过向晶片表面施加辐射能来提供选择性加热。 晶片表面的选择性加热导致晶片表面和化学镀溶液之间的界面处的温度升高。 界面处的温度升高又导致在晶片表面发生电镀反应。 因此，通过化学镀反应将材料沉积在晶片表面上，该电镀反应通过使用适当限定的辐射能源改变晶片表面的温度来启动和控制。

公开(公告)号：US06939796B2

公开(公告)日：2005-09-06

申请号：US10390117

申请日：2003-03-14

申请人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

发明人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

IPC分类号： B44C1/22 ,  H01L20060101 ,  H01L21/302 ,  H01L21/304 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768 ,  H01L33/00

CPC分类号： H01L21/7684 ,  H01L21/31116 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/32136

摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

摘要翻译： 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分具有局部不均匀性。 去除覆盖层部分的大部分以平坦化上覆层部分。 映射基本上局部平坦化的覆盖层部分以确定全局不均匀性。 基本上局部平坦化的覆盖层部分被蚀刻以基本上去除全局不均匀性。

公开(公告)号：US07875554B2

公开(公告)日：2011-01-25

申请号：US12044537

申请日：2008-03-07

申请人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

发明人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

IPC分类号： H01L21/44

CPC分类号： C23C18/1612 ,  C23C18/14 ,  C23C18/161 ,  C23C18/1619 ,  C23C18/1651 ,  C23C18/1667 ,  C23C18/168 ,  C23C18/31 ,  H01L21/288

摘要： Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

摘要翻译： 概括地说，提供了一种在半导体晶片（“晶片”）上沉积材料的方法和装置。 更具体地，该方法和装置提供了暴露于化学镀溶液的晶片的表面的选择性加热。 通过向晶片表面施加辐射能来提供选择性加热。 晶片表面的选择性加热导致晶片表面和化学镀溶液之间的界面处的温度升高。 界面处的温度升高又导致在晶片表面发生电镀反应。 因此，通过化学镀反应将材料沉积在晶片表面上，该电镀反应通过使用适当限定的辐射能源改变晶片表面的温度来启动和控制。

公开(公告)号：US07358186B2

公开(公告)日：2008-04-15

申请号：US10735216

申请日：2003-12-12

申请人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

发明人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

IPC分类号： H01L21/44 ,  B05C5/12

CPC分类号： C23C18/1612 ,  C23C18/14 ,  C23C18/161 ,  C23C18/1619 ,  C23C18/1651 ,  C23C18/1667 ,  C23C18/168 ,  C23C18/31 ,  H01L21/288

摘要： Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

摘要翻译： 概括地说，提供了一种在半导体晶片（“晶片”）上沉积材料的方法和装置。 更具体地，该方法和装置提供了暴露于化学镀溶液的晶片的表面的选择性加热。 通过向晶片表面施加辐射能来提供选择性加热。 晶片表面的选择性加热导致晶片表面和化学镀溶液之间的界面处的温度升高。 界面处的温度升高又导致在晶片表面发生电镀反应。 因此，通过化学镀反应将材料沉积在晶片表面上，该电镀反应通过使用适当限定的辐射能源改变晶片表面的温度来启动和控制。

公开(公告)号：US06165910A

公开(公告)日：2000-12-26

申请号：US998954

申请日：1997-12-29

申请人： Janet M. Flanner ,  Linda N. Marquez ,  Joel M. Cook ,  Ian J. Morey

发明人： Janet M. Flanner ,  Linda N. Marquez ,  Joel M. Cook ,  Ian J. Morey

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/60 ,  H01L21/00

CPC分类号： H01L21/76897 ,  H01L21/31116

摘要： In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.

摘要翻译： 在等离子体处理室中，描述了通过晶片层叠层的氧化物层的选定部分蚀刻以形成自对准接触开口的方法。 晶片堆叠包括基板，设置在基板上方的多晶硅层，设置在所述多晶硅层上方的氮化物层和设置在氮化物层上方的氧化物层。 蚀刻方法包括通过化学和一组工艺参数蚀刻通过层叠层的氧化物层。 化学性质基本上包括C 2 H 5 O 5和CH 2 F 2，并且一组工艺参数有助于蚀刻通过氧化物层而不产生加标蚀刻，并将氧化物层蚀刻到衬底上而不会基本上损坏氮化物层。

公开(公告)号：US06821899B2

公开(公告)日：2004-11-23

申请号：US10390520

申请日：2003-03-14

申请人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

发明人： Shrikant P. Lohokare ,  Andrew D. Bailey, III ,  David Hemker ,  Joel M. Cook

IPC分类号： H01L21311

CPC分类号： H01L21/32135 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/7684

摘要： A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

摘要翻译： 用于平坦化图案化半导体衬底的系统和方法包括接收图案化的半导体衬底。 图案化半导体衬底具有填充图案中的多个特征的导电互连材料。 导电互连材料具有覆盖层部分。 覆盖层部分包括局部不均匀性。 在覆盖层部分上形成附加层。 附加层和覆盖层部分被平坦化。 平坦化工艺基本上完全除去附加层。

公开(公告)号：US06028286A

公开(公告)日：2000-02-22

申请号：US223692

申请日：1998-12-30

申请人： Thomas E. Wicker ,  Joel M. Cook ,  Jian J. Chen

发明人： Thomas E. Wicker ,  Joel M. Cook ,  Jian J. Chen

IPC分类号： H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  B23K10/00

CPC分类号： H01J37/32009 ,  H01J37/321 ,  H01J37/3266

摘要： The invention relates to a plasma processing reactor for processing a substrate. The plasma processing reactor includes a process chamber. The plasma processing reactor further includes an inductive coil configured to be coupled to a RF power source having a RF frequency wherein the inductive coil generates an electric field inside of the process chamber. The plasma processing reactor additionally includes a magnetic field producing device configured to produce a magnetic field inside the process chamber in proximity of the electric field.

摘要翻译： 本发明涉及一种用于处理衬底的等离子体处理反应器。 等离子体处理反应器包括处理室。 等离子体处理反应器还包括被配置为耦合到具有RF频率的RF功率源的感应线圈，其中感应线圈在处理室内产生电场。 等离子体处理反应器还包括磁场产生装置，其被配置为在电场附近在处理室内产生磁场。

公开(公告)号：US5346579A

公开(公告)日：1994-09-13

申请号：US93445

申请日：1993-07-19

申请人： Joel M. Cook ,  John R. Trow

发明人： Joel M. Cook ,  John R. Trow

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  H05H1/46 ,  H01L21/00

CPC分类号： H01J37/32623 ,  H01J37/32192 ,  H01J37/32688 ,  H01J37/32743 ,  H01J2237/334

摘要： A plasma etch reactor comprising a remote source of plasma mounted on a vacuum processing chamber has a large permanent magnet ring around the area of the chamber where the plasma enters, magnetically oriented so that magnetic field lines are removed from said plasma in the processing chamber, and two or more pairs of magnet rings mounted around said chamber to form a series of magnetic cusps about the wall of said chamber, to thereby inhibit plasma electrons from striking the wall of said chamber. A substrate entry port can be fitted between the magnet rings, allowing automatic ingress and egress of said substrates with maximum efficiency.

摘要翻译： 包括安装在真空处理室上的等离子体等离子体蚀刻反应器的等离子体入口等离子体的区域周围具有大的永磁体环，磁性取向使得磁场线从处理室中的所述等离子体中除去， 以及两个或更多对安装在所述腔室周围的磁环，以形成围绕所述腔室的壁的一系列磁尖，从而抑制等离子体电子撞击所述腔室的壁。 可以在磁环之间安装基板进入口，从而最大程度地实现自动进入和离开所述基板。

公开(公告)号：US08490573B2

公开(公告)日：2013-07-23

申请号：US12968114

申请日：2010-12-14

申请人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

发明人： Yezdi Dordi ,  John Boyd ,  William Thie ,  Bob Maraschin ,  Fred C. Redeker ,  Joel M. Cook

IPC分类号： B05C3/02 ,  B05D1/18

CPC分类号： C23C18/1612 ,  C23C18/14 ,  C23C18/161 ,  C23C18/1619 ,  C23C18/1651 ,  C23C18/1667 ,  C23C18/168 ,  C23C18/31 ,  H01L21/288

摘要： Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

摘要翻译： 概括地说，提供了一种在半导体晶片（“晶片”）上沉积材料的方法和装置。 更具体地，该方法和装置提供了暴露于化学镀溶液的晶片的表面的选择性加热。 通过向晶片表面施加辐射能来提供选择性加热。 晶片表面的选择性加热导致晶片表面和化学镀溶液之间的界面处的温度升高。 界面处的温度升高又导致在晶片表面发生电镀反应。 因此，通过化学镀反应将材料沉积在晶片表面上，该电镀反应通过使用适当限定的辐射能源改变晶片表面的温度来启动和控制。