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1.发明授权Semiconductor device and method for making the device having an electrically modulated conduction channel 有权用于制造具有电调制传导通道的器件的半导体器件和方法公开(公告)号：US06683345B1
公开(公告)日：2004-01-27
申请号：US09467537
申请日：1999-12-20
申请人： Eric Adler , James S. Dunn , Joseph Iadanza , Jenifer E. Lary , Kent E. Morrett , Josef S. Watts
发明人： Eric Adler , James S. Dunn , Joseph Iadanza , Jenifer E. Lary , Kent E. Morrett , Josef S. Watts
IPC分类号： H01L2976
CPC分类号： H01L29/8605 , H01L21/823412 , H01L21/823481 , H01L27/0802 , H01L29/78 , H03M1/0604 , H03M1/66
摘要： A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.
摘要翻译： 具有电调制的导电通道的半导体器件。 在包围扩散区域的衬底内形成沟槽结构。 沟槽结构将形成在扩散区域内的器件与衬底的剩余部分隔离。 沟壁被制成足够薄，使得扩散区域内的通道的宽度可以通过在沟槽壁和衬底之间施加电势来控制。 形成在沟槽结构内的晶体管具有由所施加的电压控制的导通沟道宽度，允许晶体管的增益与衬底上的其它晶体管的增益匹配。
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公开(公告)号：US06433372B1
公开(公告)日：2002-08-13
申请号：US09527863
申请日：2000-03-17
申请人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
发明人： Eric Adler , Kerry Bernstein , John J. Ellis-Monaghan , Jenifer E. Lary , Edward J. Nowak , Norman J. Rohrer
IPC分类号： H01L2972
CPC分类号： H01L29/66484
摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.
摘要翻译： 具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。 通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层 绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。
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公开(公告)号：US20100029056A1
公开(公告)日：2010-02-04
申请号：US12181338
申请日：2008-07-29
IPC分类号： H01L21/334
CPC分类号： H01L28/90
摘要： A method of manufacturing a dual contact trench capacitor is provided. The method includes a first plate extending from a trench and isolated from a wafer body, and forming a second plate extending from the trench and isolated from the wafer body and the first plate.
摘要翻译： 提供一种制造双接触沟槽电容器的方法。 该方法包括从沟槽延伸并从晶片本体隔离的第一板，以及形成从沟槽延伸并与晶片本体和第一板隔离的第二板。
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公开(公告)号：US08198663B2
公开(公告)日：2012-06-12
申请号：US12181343
申请日：2008-07-29
IPC分类号： H01L27/108
CPC分类号： H01L28/90 , H01L29/945
摘要： A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.
摘要翻译： 提供双接触沟槽电容器和双接触沟槽电容器的设计结构。 该结构包括从沟槽延伸并与晶片本体隔离的第一板和从沟槽延伸并与晶片体和第一板分离的第二板。
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公开(公告)号：US20100029055A1
公开(公告)日：2010-02-04
申请号：US12181335
申请日：2008-07-29
IPC分类号： H01L21/02
CPC分类号： H01L27/0733 , H01L21/76229 , H01L28/90
摘要： A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench.
摘要翻译： 提供一种制造双接触沟槽电容器的方法。 该方法包括形成设置在沟槽内的第一板，并且通过形成在沟槽中的第一绝缘体层与晶片本体隔离。 该方法还包括形成设置在沟槽内的第二板，并且通过在沟槽中形成的第二绝缘体与晶片本体和第一板隔离。
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公开(公告)号：US20100025813A1
公开(公告)日：2010-02-04
申请号：US12181341
申请日：2008-07-29
IPC分类号： H01L29/92
CPC分类号： H01L28/90 , H01L29/945
摘要： A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.
摘要翻译： 提供双接触沟槽电容器和双接触沟槽电容器的设计结构。 该结构包括从沟槽延伸并与晶片本体隔离的第一板和从沟槽延伸并与晶片体和第一板分离的第二板。
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7.发明授权Single twist layout and method for paired line conductors of integrated circuits 失效集成电路成对线导体的单扭曲布局和方法
公开(公告)号：US5534732A
公开(公告)日：1996-07-09
申请号：US567437
申请日：1995-12-04
IPC分类号： H01L21/822 , G11C7/18 , H01L21/8242 , H01L23/522 , H01L27/04 , H01L27/108 , H01L27/10
CPC分类号： H01L27/108 , G11C7/18 , H01L23/5225 , H01L2924/0002 , Y10S257/907
摘要： An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.
摘要翻译： 为主要平行延伸的给定长度的多个成对线导体提供互连阵列布局和方法。 单个交叉区域穿过给定长度中间的成对线导体，其中每对线路导体的线路导体互相交叉，使得对间电容耦合相匹配。 通过将每对线路导体的线路导体分开两个间距并在其间设置不同对线路导线的线路导体来避免对内电容耦合。 应用包括诸如DRAM结构的半导体存储器阵列，以及使用配对的真/互补线导体的地址/数据总线。
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公开(公告)号：US20120018837A1
公开(公告)日：2012-01-26
申请号：US12840791
申请日：2010-07-21
IPC分类号： H01L29/872 , G06F9/45 , H01L21/329
CPC分类号： H01L29/872 , H01L21/761 , H01L29/0619 , H01L29/0646 , H01L29/0692 , H01L29/66143
摘要： A Schottky barrier diode comprises a first-type substrate, a second-type well isolation region on the first-type substrate, and a first-type well region on the second-type well isolation region. With embodiments herein a feature referred to as a perimeter capacitance well junction ring is on the second-type well isolation region. A second-type well region is on the second-type well isolation region. The perimeter capacitance well junction ring is positioned between and separates the first-type well region and the second-type well region. A second-type contact region is on the second-type well region, and a first-type contact region contacts the inner portion of the first-type well region. The inner portion of the first-type well region is positioned within the center of the first-type contact region. Additionally, a first ohmic metallic layer is on the first-type contact region and a second ohmic metallic layer is on the first-type well region. The first ohmic metallic layer contacts the second ohmic metallic layer at a junction that makes up the Schottky barrier of the Schottky barrier diode.
摘要翻译： 肖特基势垒二极管包括第一类型衬底，第一类型衬底上的第二类型阱隔离区域和第二类型阱隔离区域上的第一类型阱区域。 在这里的实施例中，被称为周边电容阱接合环的特征在第二类型的隔离区域上。 第二类型井区域位于第二类型井隔离区域上。 周边电容阱接合环位于第一类型阱区域和第二类型阱区域之间并分离。 第二类型接触区域位于第二类型阱区域上，并且第一类型接触区域接触第一类型阱区域的内部部分。 第一类型阱区域的内部位于第一类型接触区域的中心内。 此外，第一欧姆金属层位于第一类型接触区域上，第二欧姆金属层位于第一类型阱区域上。 第一欧姆金属层在构成肖特基势垒二极管的肖特基势垒的结处接触第二欧姆金属层。
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公开(公告)号：US07897473B2
公开(公告)日：2011-03-01
申请号：US12181335
申请日：2008-07-29
IPC分类号： H01L21/20
CPC分类号： H01L27/0733 , H01L21/76229 , H01L28/90
摘要： A method of manufacturing a dual contact trench capacitor is provided. The method includes forming a first plate provided within a trench and isolated from a wafer body by a first insulator layer formed in the trench. The method further includes forming a second plate provided within the trench and isolated from the wafer body and the first plate by a second insulator layer formed in the trench.
摘要翻译： 提供一种制造双接触沟槽电容器的方法。 该方法包括形成设置在沟槽内的第一板，并且通过形成在沟槽中的第一绝缘体层与晶片本体隔离。 该方法还包括形成设置在沟槽内的第二板，并且通过在沟槽中形成的第二绝缘体与晶片本体和第一板隔离。
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公开(公告)号：US20100025814A1
公开(公告)日：2010-02-04
申请号：US12181343
申请日：2008-07-29
CPC分类号： H01L28/90 , H01L29/945
摘要： A dual contact trench capacitor and design structure for a dual contact trench capacitor is provided. The structure includes a first plate extending from a trench and isolated from a wafer body, and a second plate extending from the trench and isolated from the wafer body and the first plate.
摘要翻译： 提供双接触沟槽电容器和双接触沟槽电容器的设计结构。 该结构包括从沟槽延伸并与晶片本体隔离的第一板和从沟槽延伸并与晶片体和第一板分离的第二板。
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