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113 条记录 (耗时 0.057 秒)

    Single twist layout and method for paired line conductors of integrated circuits
    1.
    发明授权
    Single twist layout and method for paired line conductors of integrated circuits 失效
    集成电路成对线导体的单扭曲布局和方法

    公开(公告)号：US5534732A

    公开(公告)日：1996-07-09

    申请号：US567437

    申请日：1995-12-04

    申请人： John K. DeBrosse ,  Jenifer E. Lary ,  Edmund J. Sprogis

    发明人： John K. DeBrosse ,  Jenifer E. Lary ,  Edmund J. Sprogis

    IPC分类号： H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10

    CPC分类号： H01L27/108 ,  G11C7/18 ,  H01L23/5225 ,  H01L2924/0002 ,  Y10S257/907

    摘要： An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

    摘要翻译： 为主要平行延伸的给定长度的多个成对线导体提供互连阵列布局和方法。 单个交叉区域穿过给定长度中间的成对线导体，其中每对线路导体的线路导体互相交叉，使得对间电容耦合相匹配。 通过将每对线路导体的线路导体分开两个间距并在其间设置不同对线路导线的线路导体来避免对内电容耦合。 应用包括诸如DRAM结构的半导体存储器阵列，以及使用配对的真/互补线导体的地址/数据总线。

    Coil inductor for on-chip or on-chip stack
    3.
    发明授权
    Coil inductor for on-chip or on-chip stack 有权
    用于片上或片上堆叠的线圈电感

    公开(公告)号：US09105627B2

    公开(公告)日：2015-08-11

    申请号：US13289071

    申请日：2011-11-04

    申请人： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    发明人： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    IPC分类号： H01F5/00 ,  H01L27/08 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/00

    CPC分类号： H01L23/49822 ,  H01F17/0013 ,  H01F41/005 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

    摘要： A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

    摘要翻译： 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。

    Through wafer vias with dishing correction methods
    7.
    发明授权
    Through wafer vias with dishing correction methods 有权
    通过具有凹陷校正方法的晶片通孔

    公开(公告)号：US08631570B2

    公开(公告)日：2014-01-21

    申请号：US13369414

    申请日：2012-02-09

    申请人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    发明人： Peter J. Lindgren ,  Edmund J. Sprogis ,  Anthony K. Stamper

    IPC分类号： H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H01L29/40

    CPC分类号： H01L21/76898 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

    摘要翻译： 提出了通过晶片通孔（TWV）和标准触点在两个单独的工艺中形成以防止铜第一金属层挤压和短路的方法。 在一个实施例中，一种方法可以包括将TWV形成到衬底上并且在衬底上形成第一介电层; 在所述衬底和所述TWV上形成第二电介质层; 通过所述第二电介质层形成至少一个接触到所述TWV和与所述衬底上的其它结构的至少一个接触; 以及在所述第二电介质层上形成第一金属布线层，所述第一金属布线层与所述触点中的至少一个接触。