公开(公告)号：US06683345B1

公开(公告)日：2004-01-27

申请号：US09467537

申请日：1999-12-20

申请人： Eric Adler ,  James S. Dunn ,  Joseph Iadanza ,  Jenifer E. Lary ,  Kent E. Morrett ,  Josef S. Watts

发明人： Eric Adler ,  James S. Dunn ,  Joseph Iadanza ,  Jenifer E. Lary ,  Kent E. Morrett ,  Josef S. Watts

IPC分类号： H01L2976

CPC分类号： H01L29/8605 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0802 ,  H01L29/78 ,  H03M1/0604 ,  H03M1/66

摘要： A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.

摘要翻译： 具有电调制的导电通道的半导体器件。 在包围扩散区域的衬底内形成沟槽结构。 沟槽结构将形成在扩散区域内的器件与衬底的剩余部分隔离。 沟壁被制成足够薄，使得扩散区域内的通道的宽度可以通过在沟槽壁和衬底之间施加电势来控制。 形成在沟槽结构内的晶体管具有由所施加的电压控制的导通沟道宽度，允许晶体管的增益与衬底上的其它晶体管的增益匹配。

公开(公告)号：US06476483B1

公开(公告)日：2002-11-05

申请号：US09421910

申请日：1999-10-20

申请人： Eric Adler ,  James S. Dunn ,  Kent E. Morrett ,  Edward J. Nowak ,  Stephen A. St. Onge

发明人： Eric Adler ,  James S. Dunn ,  Kent E. Morrett ,  Edward J. Nowak ,  Stephen A. St. Onge

IPC分类号： H01L2334

CPC分类号： H01L29/66772 ,  H01L23/38 ,  H01L29/41733 ,  H01L29/458 ,  H01L2924/0002 ,  Y10S257/93 ,  H01L2924/00

摘要： In an electronic device with an active region on top of and isolated from an substrate, a first material region is defined on top of and/or adjacent to and electrically isolated from the active region and a second material region is attached to a surface of the first material region to form an interface defining a Peltier cooling junction therebetween. A current source connected in series to the first and the second material regions produces a cooling effect at the Peltier cooling junction.

摘要翻译： 在具有有源区域在基板之上和与衬底隔离的电子器件中，第一材料区域被限定在与有源区域之间和/或邻近并与其隔离的第一材料区域，并且第二材料区域附接到 第一材料区域以形成在它们之间限定珀尔贴冷却接头的界面。 与第一和第二材料区域串联连接的电流源在珀尔帖冷却结处产生冷却效果。

公开(公告)号：US20130256758A1

公开(公告)日：2013-10-03

申请号：US13436045

申请日：2012-03-30

申请人： Renata A. Camillo-Castillo ,  James S. Dunn ,  David L. Harame ,  Anthony K. Stamper

发明人： Renata A. Camillo-Castillo ,  James S. Dunn ,  David L. Harame ,  Anthony K. Stamper

IPC分类号： H01L29/737 ,  H01L21/764

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/764 ,  H01L29/737

摘要： A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.

摘要翻译： 形成集成电路结构的方法包括：通过延伸通过浅沟槽隔离（STI）形成通气孔并进入衬底; 在所述通气孔的底部选择性地去除所述衬底的暴露部分以在所述衬底内形成开口，其中所述衬底内的所述开口邻接所述STI的底表面或侧壁中的至少一个; 并密封通气孔以在基底内的开口中形成气隙。

公开(公告)号：US20130140668A1

公开(公告)日：2013-06-06

申请号：US13312442

申请日：2011-12-06

申请人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

发明人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

IPC分类号： H01L27/04 ,  H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US07776704B2

公开(公告)日：2010-08-17

申请号：US11830376

申请日：2007-07-30

申请人： James S. Dunn ,  Alvin J. Joseph ,  Qizhi Liu

发明人： James S. Dunn ,  Alvin J. Joseph ,  Qizhi Liu

IPC分类号： H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

公开(公告)号：US07253096B2

公开(公告)日：2007-08-07

申请号：US11289915

申请日：2005-11-30

申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

IPC分类号： H01L21/4763

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

公开(公告)号：US06906401B2

公开(公告)日：2005-06-14

申请号：US10856503

申请日：2004-05-28

申请人： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

发明人： James S. Dunn ,  Natalie B. Feilchenfeld ,  Qizhi Liu ,  Andreas D. Stricker

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/737 ,  H01L29/72

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/7378

摘要： A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.

摘要翻译： 提供了一种形成表现出高性能的准自对准异质结双极晶体管（HBT）的方法。 该方法包括使用图案化的发射器着陆焊盘叠层，其用于改进发射极开口光刻的对准以及用于发射极开口蚀刻的蚀刻停止层。 本发明还提供了一种HBT，其包括具有位于发射器着陆焊盘堆叠下方的单晶区域的凸起的外部基极。

公开(公告)号：US09424992B2

公开(公告)日：2016-08-23

申请号：US13427216

申请日：2012-03-22

申请人： James S. Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

发明人： James S. Dunn ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC分类号： H01G4/33 ,  H01G4/38 ,  H01G4/12 ,  H01G4/232 ,  H01L23/522 ,  H01L49/02 ,  H01L27/08

CPC分类号： H01G4/33 ,  H01G4/1209 ,  H01G4/232 ,  H01G4/38 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49156 ,  H01L2924/00

摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.

摘要翻译： 同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。 该方法包括在电介质材料上沉积底板; 在底板上沉积低k电介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器 第一厚度。

公开(公告)号：US08735986B2

公开(公告)日：2014-05-27

申请号：US13312442

申请日：2011-12-06

申请人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

发明人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Robert M. Rassel ,  Mark E. Stidham

IPC分类号： H01L27/12

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。

公开(公告)号：US08674472B2

公开(公告)日：2014-03-18

申请号：US12853532

申请日：2010-08-10

申请人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

发明人： Alan B. Botula ,  Dinh Dang ,  James S. Dunn ,  Alvin J. Joseph ,  Peter J. Lindgren

IPC分类号： H01L21/764

CPC分类号： H01L21/76283 ,  H01L21/76289 ,  H01L27/0738 ,  H01L27/1203 ,  H01L29/0649

摘要： A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.