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    OPTICALLY ENABLED MULTI-CHIP MODULES
    1.
    发明申请
    OPTICALLY ENABLED MULTI-CHIP MODULES 有权
    光纤启用多芯片模块

    公开(公告)号：US20150090864A1

    公开(公告)日：2015-04-02

    申请号：US14500212

    申请日：2014-09-29

    Applicant: FINISAR CORPORATION

    Inventor： Frank J. Flens ,  Daniel Mahgerefteh ,  The' Linh Nguyen ,  Jimmy Alan Tatum

    IPC: H04B10/40

    CPC classification number: H04B10/40 ,  H04B10/502 ,  H04B10/801

    Abstract: An optically enabled multi-chip module has an optical engine transceiver and a host system chip. The optical engine transceiver has an optical engine front-end and an optical engine macro. The optical engine front-end has multiple laser diodes, laser driver circuitry electrically interfaced with each of the laser diodes, multiple photodiodes, amplifier circuitry electrically interfaced with each of the photodiodes, and at least one optical element optically positioned between the laser diodes and at least one optical fiber and between the photodiodes and the at least one optical fiber. The at least one optical element optically interfaces the laser diodes and photodiodes with the optical fiber. The optical engine macro is both electrically interfaced with and physically segregated from the optical engine front-end. The optical engine macro provides a subset of optical transceiver functionality to the optical engine front-end. The host system chip is electrically interfaced with the optical engine transceiver.

    Abstract translation: 光学启用的多芯片模块具有光学引擎收发器和主机系统芯片。 光引擎收发器具有光引擎前端和光引擎宏。 光学引擎前端具有多个激光二极管，与每个激光二极管电连接的激光驱动器电路，多个光电二极管，与每个光电二极管电连接的放大器电路，以及光学定位在激光二极管之间的至少一个光学元件 至少一个光纤，并且在所述光电二极管和所述至少一个光纤之间。 所述至少一个光学元件将激光二极管和光电二极管与光纤光学接口。 光学引擎宏与光引擎前端电接口并与之物理隔离。 光学引擎宏为光引擎前端提供光收发器功能的子集。 主机系统芯片与光引擎收发器电接口。

    Optically enabled multi-chip modules including optical engine macros
    3.
    发明授权
    Optically enabled multi-chip modules including optical engine macros 有权

    公开(公告)号：US10594402B2

    公开(公告)日：2020-03-17

    申请号：US15369770

    申请日：2016-12-05

    Applicant: FINISAR CORPORATION

    Inventor： Frank J. Flens ,  Daniel Mahgerefteh ,  The' Linh Nguyen ,  Jimmy Alan Tatum

    IPC: H04B10/40 ,  H04B10/80 ,  H04B10/50

    Abstract: An optically enabled multi-chip module has an optical engine transceiver and a host system chip. The optical engine transceiver has an optical engine front-end and an optical engine macro. The optical engine front-end has multiple laser diodes, laser driver circuitry electrically interfaced with each of the laser diodes, multiple photodiodes, amplifier circuitry electrically interfaced with each of the photodiodes, and at least one optical element optically positioned between the laser diodes and at least one optical fiber and between the photodiodes and the at least one optical fiber. The at least one optical element optically interfaces the laser diodes and photodiodes with the optical fiber. The optical engine macro is both electrically interfaced with and physically segregated from the optical engine front-end. The optical engine macro provides a subset of optical transceiver functionality to the optical engine front-end. The host system chip is electrically interfaced with the optical engine transceiver.

    OPTICALLY ENABLED MULTI-CHIP MODULES
    6.
    发明申请
    OPTICALLY ENABLED MULTI-CHIP MODULES 审中-公开

    公开(公告)号：US20170237496A1

    公开(公告)日：2017-08-17

    申请号：US15369770

    申请日：2016-12-05

    Applicant: FINISAR CORPORATION

    Inventor： Frank J. Flens ,  Daniel Mahgerefteh ,  The' Linh Nguyen ,  Jimmy Alan Tatum

    IPC: H04B10/40 ,  H04B10/50 ,  H04B10/80

    CPC classification number: H04B10/40 ,  H04B10/502 ,  H04B10/801

    Abstract: An optically enabled multi-chip module has an optical engine transceiver and a host system chip. The optical engine transceiver has an optical engine front-end and an optical engine macro. The optical engine front-end has multiple laser diodes, laser driver circuitry electrically interfaced with each of the laser diodes, multiple photodiodes, amplifier circuitry electrically interfaced with each of the photodiodes, and at least one optical element optically positioned between the laser diodes and at least one optical fiber and between the photodiodes and the at least one optical fiber. The at least one optical element optically interfaces the laser diodes and photodiodes with the optical fiber. The optical engine macro is both electrically interfaced with and physically segregated from the optical engine front-end. The optical engine macro provides a subset of optical transceiver functionality to the optical engine front-end. The host system chip is electrically interfaced with the optical engine transceiver.

    INTEGRATED POWER SUPPLY FOR FIBER OPTIC COMMUNICATION DEVICES AND SUBSYSTEMS
    7.
    发明申请
    INTEGRATED POWER SUPPLY FOR FIBER OPTIC COMMUNICATION DEVICES AND SUBSYSTEMS 有权
    用于光纤通信设备和子系统的集成电源

    公开(公告)号：US20160322961A1

    公开(公告)日：2016-11-03

    申请号：US15090614

    申请日：2016-04-04

    Applicant: FINISAR CORPORATION

    Inventor： Henry M. Daghighian ,  Luke M. Ekkizogloy ,  The' Linh Nguyen ,  Christopher Kocot ,  James Prettyleaf

    IPC: H03K3/013 ,  H03K7/08 ,  H04B10/40 ,  H03K19/21

    CPC classification number: H03K3/013 ,  H03K7/08 ,  H03K19/21 ,  H04B10/40

    Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

    Abstract translation: 示例实施例包括光纤集成电路（IC）。 光纤IC包括集成电源。 集成电源包括滤波器，有源开关和脉宽调制器（“PWM”）。 滤波器被配置为将信号转换成集成电源的输出信号。 有源开关被配置为控制信号到滤波器的引入。 PWM被配置为产生触发有源开关的PWM输出信号。

    Clock recovery and equalizer estimation in a multi-channel receiver
    9.
    发明授权
    Clock recovery and equalizer estimation in a multi-channel receiver 有权
    多通道接收机中的时钟恢复和均衡器估计

    公开(公告)号：US09590799B2

    公开(公告)日：2017-03-07

    申请号：US14664810

    申请日：2015-03-21

    Applicant: Finisar Corporation

    Inventor： Ilya Lyubomirsky ,  The' Linh Nguyen

    IPC: H04B10/69 ,  H04L7/00 ,  H04L25/03 ,  H04L25/14

    CPC classification number: H04L7/0075 ,  H04L7/0004 ,  H04L25/03 ,  H04L25/03006 ,  H04L25/14

    Abstract: A method of performing clock recovery and equalizer coefficient estimation in a multi-channel receiver may include recovering, at a first clock recovery unit, a first clock signal associated with a first channel. The method may include estimating a first set of coefficients for a first equalizer associated with the first channel using the first clock signal. The method may include passing the first clock signal to a second clock recovery unit associated with a second channel. The method may also include recovering, at the second clock recovery unit, a second clock signal associated with the second channel using the first clock signal as a reference clock signal. The method may also include passing the first set of coefficients as initialization coefficients to a second equalizer associated with the second channel. The method may also include estimating a second set of coefficients for the second equalizer using the initialization coefficients.

    Abstract translation: 在多信道接收机中执行时钟恢复和均衡器系数估计的方法可包括在第一时钟恢复单元处恢复与第一信道相关联的第一时钟信号。 该方法可以包括使用第一时钟信号估计与第一信道相关联的第一均衡器的第一组系数。 该方法可以包括将第一时钟信号传递到与第二信道相关联的第二时钟恢复单元。 该方法还可以包括使用第一时钟信号作为参考时钟信号在第二时钟恢复单元处恢复与第二信道相关联的第二时钟信号。 该方法还可以包括将第一组系数作为初始化系数传递到与第二信道相关联的第二均衡器。 该方法还可以包括使用初始化系数来估计第二均衡器的第二组系数。

    Clock Recovery and Equalizer Estimation In a Multi-Channel Receiver
    10.
    发明申请
    Clock Recovery and Equalizer Estimation In a Multi-Channel Receiver 有权
    多通道接收机中的时钟恢复和均衡器估计

    公开(公告)号：US20160277175A1

    公开(公告)日：2016-09-22

    申请号：US14664810

    申请日：2015-03-21

    Applicant: Finisar Corporation

    Inventor： Ilya Lyubomirsky ,  The' Linh Nguyen

    IPC: H04L7/00 ,  H04L25/03

    CPC classification number: H04L7/0075 ,  H04L7/0004 ,  H04L25/03 ,  H04L25/03006 ,  H04L25/14

    Abstract: A method of performing clock recovery and equalizer coefficient estimation in a multi-channel receiver may include recovering, at a first clock recovery unit, a first clock signal associated with a first channel. The method may include estimating a first set of coefficients for a first equalizer associated with the first channel using the first clock signal. The method may include passing the first clock signal to a second clock recovery unit associated with a second channel. The method may also include recovering, at the second clock recovery unit, a second clock signal associated with the second channel using the first clock signal as a reference clock signal. The method may also include passing the first set of coefficients as initialization coefficients to a second equalizer associated with the second channel. The method may also include estimating a second set of coefficients for the second equalizer using the initialization coefficients.

    Abstract translation: 在多信道接收机中执行时钟恢复和均衡器系数估计的方法可包括在第一时钟恢复单元处恢复与第一信道相关联的第一时钟信号。 该方法可以包括使用第一时钟信号估计与第一信道相关联的第一均衡器的第一组系数。 该方法可以包括将第一时钟信号传递到与第二信道相关联的第二时钟恢复单元。 该方法还可以包括使用第一时钟信号作为参考时钟信号在第二时钟恢复单元处恢复与第二信道相关联的第二时钟信号。 该方法还可以包括将第一组系数作为初始化系数传递到与第二信道相关联的第二均衡器。 该方法还可以包括使用初始化系数来估计第二均衡器的第二组系数。

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