Abstract:
An optically enabled multi-chip module has an optical engine transceiver and a host system chip. The optical engine transceiver has an optical engine front-end and an optical engine macro. The optical engine front-end has multiple laser diodes, laser driver circuitry electrically interfaced with each of the laser diodes, multiple photodiodes, amplifier circuitry electrically interfaced with each of the photodiodes, and at least one optical element optically positioned between the laser diodes and at least one optical fiber and between the photodiodes and the at least one optical fiber. The at least one optical element optically interfaces the laser diodes and photodiodes with the optical fiber. The optical engine macro is both electrically interfaced with and physically segregated from the optical engine front-end. The optical engine macro provides a subset of optical transceiver functionality to the optical engine front-end. The host system chip is electrically interfaced with the optical engine transceiver.
Abstract:
A system includes a surface coupled edge emitting laser that includes a core waveguide, a fan out region optically coupled to the core waveguide in a same layer of the surface coupled edge emitting laser as the core waveguide; and a first surface grating formed in the fan out region; and a photonic integrated circuit (PIC) that includes an optical waveguide and a second surface grating formed in an upper layer of the PIC, wherein the second surface grating is in optical alignment with the first surface grating.
Abstract:
An optically enabled multi-chip module has an optical engine transceiver and a host system chip. The optical engine transceiver has an optical engine front-end and an optical engine macro. The optical engine front-end has multiple laser diodes, laser driver circuitry electrically interfaced with each of the laser diodes, multiple photodiodes, amplifier circuitry electrically interfaced with each of the photodiodes, and at least one optical element optically positioned between the laser diodes and at least one optical fiber and between the photodiodes and the at least one optical fiber. The at least one optical element optically interfaces the laser diodes and photodiodes with the optical fiber. The optical engine macro is both electrically interfaced with and physically segregated from the optical engine front-end. The optical engine macro provides a subset of optical transceiver functionality to the optical engine front-end. The host system chip is electrically interfaced with the optical engine transceiver.
Abstract:
A system includes a surface coupled edge emitting laser that includes a core waveguide, a fan out region optically coupled to the core waveguide in a same layer of the surface coupled edge emitting laser as the core waveguide; and a first surface grating formed in the fan out region; and a photonic integrated circuit (PIC) that includes an optical waveguide and a second surface grating formed in an upper layer of the PIC, wherein the second surface grating is in optical alignment with the first surface grating.
Abstract:
A system includes a surface coupled edge emitting laser that includes a core waveguide, a fan out region optically coupled to the core waveguide in a same layer of the surface coupled edge emitting laser as the core waveguide; and a first surface grating formed in the fan out region; and a photonic integrated circuit (PIC) that includes an optical waveguide and a second surface grating formed in an upper layer of the PIC, wherein the second surface grating is in optical alignment with the first surface grating.
Abstract:
An optically enabled multi-chip module has an optical engine transceiver and a host system chip. The optical engine transceiver has an optical engine front-end and an optical engine macro. The optical engine front-end has multiple laser diodes, laser driver circuitry electrically interfaced with each of the laser diodes, multiple photodiodes, amplifier circuitry electrically interfaced with each of the photodiodes, and at least one optical element optically positioned between the laser diodes and at least one optical fiber and between the photodiodes and the at least one optical fiber. The at least one optical element optically interfaces the laser diodes and photodiodes with the optical fiber. The optical engine macro is both electrically interfaced with and physically segregated from the optical engine front-end. The optical engine macro provides a subset of optical transceiver functionality to the optical engine front-end. The host system chip is electrically interfaced with the optical engine transceiver.
Abstract:
An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.
Abstract:
A multi-channel receiver that includes a first clock recovery unit configured to recover a first clock signal associated with a first optical channel is disclosed. A first coefficient estimation unit estimates a first set of coefficients using the first clock signal. A second clock recovery unit configured to recover a second clock signal associated with a second optical channel using the first clock signal as a reference clock signal. A second coefficient estimation unit estimates a second set of coefficients using the first set of coefficients.
Abstract:
A method of performing clock recovery and equalizer coefficient estimation in a multi-channel receiver may include recovering, at a first clock recovery unit, a first clock signal associated with a first channel. The method may include estimating a first set of coefficients for a first equalizer associated with the first channel using the first clock signal. The method may include passing the first clock signal to a second clock recovery unit associated with a second channel. The method may also include recovering, at the second clock recovery unit, a second clock signal associated with the second channel using the first clock signal as a reference clock signal. The method may also include passing the first set of coefficients as initialization coefficients to a second equalizer associated with the second channel. The method may also include estimating a second set of coefficients for the second equalizer using the initialization coefficients.
Abstract:
A method of performing clock recovery and equalizer coefficient estimation in a multi-channel receiver may include recovering, at a first clock recovery unit, a first clock signal associated with a first channel. The method may include estimating a first set of coefficients for a first equalizer associated with the first channel using the first clock signal. The method may include passing the first clock signal to a second clock recovery unit associated with a second channel. The method may also include recovering, at the second clock recovery unit, a second clock signal associated with the second channel using the first clock signal as a reference clock signal. The method may also include passing the first set of coefficients as initialization coefficients to a second equalizer associated with the second channel. The method may also include estimating a second set of coefficients for the second equalizer using the initialization coefficients.