公开(公告)号：US20180082915A1

公开(公告)日：2018-03-22

申请号：US15269629

申请日：2016-09-19

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： LAKSHMINARAYAN VISWANATHAN ,  JAYNAL A. MOLLA ,  DAVID ABDO ,  MALI MAHALINGAM ,  CARL D'ACOSTA

IPC: H01L23/20 ,  H01L23/047 ,  H01L21/48 ,  H01L23/057 ,  H01L23/367 ,  B22F3/10 ,  B22F1/00 ,  B23K35/02 ,  B23K35/30

CPC classification number: H01L23/20 ,  B22F1/0062 ,  B22F3/10 ,  B22F5/10 ,  B22F7/02 ,  B22F2301/10 ,  B22F2301/255 ,  B22F2302/45 ,  B23K35/025 ,  B23K35/30 ,  H01L21/4817 ,  H01L21/50 ,  H01L23/04 ,  H01L23/047 ,  H01L23/057 ,  H01L23/10 ,  H01L23/3675 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/73265 ,  H01L2924/01042 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.

公开(公告)号：US20160150632A1

公开(公告)日：2016-05-26

申请号：US14549934

申请日：2014-11-21

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： LAKSHMINARAYAN VISWANATHAN ,  AUDEL A. SANCHEZ ,  FERNANDO A. SANTOS ,  JERRY L. WHITE

IPC: H05K1/02 ,  H05K3/30 ,  H05K3/28 ,  H05K1/18

CPC classification number: H05K3/284 ,  H01L21/56 ,  H01L23/22 ,  H01L23/28 ,  H01L31/0203 ,  H01L31/048 ,  H01L33/52 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/73227 ,  H01L2224/73267 ,  H01L2224/92164 ,  H01L2224/92244 ,  H05K1/185 ,  H05K3/3421 ,  H05K9/0052 ,  H05K9/0081 ,  H05K2201/10166 ,  H05K2201/10371 ,  H05K2201/10977 ,  H05K2203/1316 ,  H05K2203/1327

Abstract: An embodiment of an electronic device includes a circuit component (e.g., a transistor or other component) coupled to the top surface of a substrate. Encapsulation is formed over the substrate and the component. An opening in the encapsulation extends from the encapsulation top surface to a conductive feature on the top surface of the component. A conductive termination structure within the encapsulation opening extends from the conductive feature to the encapsulation top surface. The device also may include a second circuit physically coupled to the encapsulation top surface and electrically coupled to the component through the conductive termination structure. In an alternate embodiment, the conductive termination structure may be located in a trench in the encapsulation that extends between two circuits that are embedded within the encapsulation, where the conductive termination structure is configured to reduce electromagnetic coupling between the two circuits during device operation.

Abstract translation: 电子设备的实施例包括耦合到衬底的顶表面的电路部件（例如，晶体管或其他部件）。 在衬底和组件上形成封装。 封装中的开口从封装顶表面延伸到元件顶表面上的导电特征。 封装开口内的导电端接结构从导电特征延伸到封装顶表面。 器件还可以包括物理耦合到封装顶表面的第二电路，并且通过导电端接结构电耦合到部件。 在替代实施例中，导电端接结构可以位于封装中的沟槽中，该沟槽在嵌入封装内的两个电路之间延伸，其中导电端接结构被配置为在器件操作期间减小两个电路之间的电磁耦合。

公开(公告)号：US20140252586A1

公开(公告)日：2014-09-11

申请号：US14287141

申请日：2014-05-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： JIN-WOOK JANG ,  LALGUDI M. MAHALINGAM ,  AUDEL A. SANCHEZ ,  LAKSHMINARAYAN VISWANATHAN

IPC: H01L23/373 ,  H01L23/00

CPC classification number: H01L23/373 ,  H01L23/057 ,  H01L23/3731 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0489 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Abstract translation: 半导体器件的实施例包括基板的主要部分，管芯和管芯与基板的主要部分之间的管芯附着层。 管芯附着层包括金界面层，其包含金和金中的多个第一沉淀物。 每个第一沉淀物包括镍，钴，钯，金和硅的组合。

公开(公告)号：US20180033716A1

公开(公告)日：2018-02-01

申请号：US15223307

申请日：2016-07-29

Applicant: FREESCALE SEMICONDUCTOR INC.

Inventor： LAKSHMINARAYAN VISWANATHAN

IPC: H01L23/373 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/3735 ,  B22F5/006 ,  B22F7/04 ,  B22F7/08 ,  B22F2007/042 ,  B22F2999/00 ,  B32B15/01 ,  H01L21/4882 ,  H01L23/057 ,  H01L23/3736 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/73265 ,  B22F1/0059 ,  B22F3/1121

Abstract: Methods for producing multilayer heat sinks utilizing low temperature sintering processes are provided. In one embodiment, the method includes forming a metal particle-containing precursor layer over a first principal surface of a first metal layer. The first metal layer and the metal particle-containing layer are then arranged in a stacked relationship with a second metal layer such that the precursor layer is disposed between the first and second metal layers. A low temperature sintering process is then carried-out at a maximum process temperature less than a melt point of the metal particles to transform the precursor layer into a sintered bond layer joining the first and second metal layers in a sintered multilayer heat sink. In embodiments wherein the sintered multilayer heat sink is contained within a heat sink panel, singulation may be carried-out to separate the sintered multilayer heat sink from the other heat sinks within the panel.

公开(公告)号：US20150333031A1

公开(公告)日：2015-11-19

申请号：US14808779

申请日：2015-07-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： LAKSHMINARAYAN VISWANATHAN ,  L.M. MAHALINGAM ,  DAVID F. ABDO ,  JAYNAL A. MOLLA

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20140256091A1

公开(公告)日：2014-09-11

申请号：US14287142

申请日：2014-05-26

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： JIN-WOOK JANG ,  LALGUDI M. MAHALINGAM ,  AUDEL A. SANCHEZ ,  LAKSHMINARAYAN VISWANATHAN

IPC: H01L23/00

CPC classification number: H01L23/373 ,  H01L23/057 ,  H01L23/3731 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0489 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Abstract translation: 用于形成包括管芯和衬底的半导体器件的方法的实施例包括将管芯和衬底压在一起，使得第一金层和一个或多个另外的材料层位于管芯和衬底之间，并且执行接合操作 在管芯和衬底之间形成管芯附着层。 管芯附着层包括金界面层，其包含金和金中的多个第一沉淀物。 每个第一沉淀物包括镍，钴，钯，金和硅的组合。