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公开(公告)号：US20050041498A1
公开(公告)日：2005-02-24
申请号：US10870694
申请日：2004-06-16
CPC分类号： G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.
摘要翻译： 一种相变型存储器件，其中存储器单元具有可在存储器单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件。 写入级连接到存储单元，并且具有被配置为产生没有恒定部分的放电电流并使存储器单元改变状态的电容电路。
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公开(公告)号：US09318699B2
公开(公告)日：2016-04-19
申请号：US13352680
申请日：2012-01-18
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1641 , H01L45/165 , H01L45/1675 , H01L45/1683
摘要： Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.
摘要翻译： 本文描述了电阻记忆单元结构和方法。 一个或多个存储单元结构包括包含第一电阻可变材料的第一电阻式存储单元和包括不同于第一电阻可变材料的第二电阻可变材料的第二电阻式存储单元。
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公开(公告)号：US20130181183A1
公开(公告)日：2013-07-18
申请号：US13352680
申请日：2012-01-18
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/141 , H01L45/144 , H01L45/16 , H01L45/1641 , H01L45/165 , H01L45/1675 , H01L45/1683
摘要： Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.
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公开(公告)号：US07483296B2
公开(公告)日：2009-01-27
申请号：US11233464
申请日：2005-09-22
IPC分类号： G11C11/36
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/76 , G11C2213/79
摘要： A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.
摘要翻译： 提出了一种存储器件。 存储器件包括多个存储器单元，其中每个存储器单元包括存储元件和用于在读取操作或编程操作期间选择相应的存储元件的选择器。 选择器包括单极元件和双极元件。 存储器件还包括控制装置，用于在编程操作期间在读取操作或双极元件期间普遍使能单极元件。
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公开(公告)号：US20060062051A1
公开(公告)日：2006-03-23
申请号：US11233464
申请日：2005-09-22
IPC分类号： G11C7/10
CPC分类号： G11C13/0004 , G11C13/003 , G11C2213/76 , G11C2213/79
摘要： A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.
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公开(公告)号：US08553453B2
公开(公告)日：2013-10-08
申请号：US12442392
申请日：2007-07-26
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
摘要翻译： 一种具有由相变存储元件（3）和选择开关（4）形成的存储单元（2）的相变存储器件。 由自己的相变存储元件（3）和自己的选择开关（4）形成的参考单元（2a）与待读取的存储单元组（7）相关联。 将该组存储器单元的电量与参考单元的类似电量进行比较，由此补偿存储单元的特性中的任何漂移。
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公开(公告)号：US07075841B2
公开(公告)日：2006-07-11
申请号：US10870694
申请日：2004-06-16
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.
摘要翻译： 一种相变型存储器件，其中存储器单元具有可在存储器单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件。 写入级连接到存储单元，并且具有被配置为产生没有恒定部分的放电电流并使存储器单元改变状态的电容电路。
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公开(公告)号：US06816404B2
公开(公告)日：2004-11-09
申请号：US10319439
申请日：2002-12-12
IPC分类号： G11C700
CPC分类号： G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.
摘要翻译： 相变非易失性存储器阵列由在彼此正交的第一和第二方向上延伸的多个存储单元形成。 多个列选择线平行于第一方向延伸。 多个字选择线平行于第二方向延伸。 每个存储单元包括PCM存储元件和选择晶体管。 选择晶体管的第一端子连接到PCM存储元件的第一端子，并且选择晶体管的控制端子连接到相应的字选择线。 PCM存储元件的第二端子连接到相应的列选择线，并且在读取和编程存储器单元的同时，选择晶体管的第二端子连接到参考电位区域。
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公开(公告)号：US08945403B2
公开(公告)日：2015-02-03
申请号：US13458048
申请日：2012-04-27
申请人： Fabio Pellizzer , Innocenzo Tortorelli , Christina Papagianni , Gianpaolo Spadini , Jong Won Lee
发明人： Fabio Pellizzer , Innocenzo Tortorelli , Christina Papagianni , Gianpaolo Spadini , Jong Won Lee
IPC分类号： H01B13/00
CPC分类号： G01N27/04 , H01L22/34 , H01L43/10 , H01L45/04 , H01L45/06 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material.
摘要翻译： 本文描述了具有悬臂部分的材料测试结构及其形成方法。 作为示例，形成材料测试结构的方法包括在第一介电材料中形成多个电极部分，在第一电介质材料上形成第二电介质材料，其中第二电介质材料包括第一悬臂部分和第二悬臂 并且在电极部分，第一介电材料和第二介电材料的数量上形成测试材料。
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10.发明授权Double patterning method for creating a regular array of pillars with dual shallow trench isolation 有权双重图案化方法，用于创建具有双浅沟槽隔离的规则的柱状阵列公开(公告)号：US08921196B2
公开(公告)日：2014-12-30
申请号：US13132602
申请日：2008-12-30
IPC分类号： H01L27/102 , H01L27/24 , H01L21/033 , H01L45/00
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
摘要翻译： 公开了用于形成垂直双极结晶体管的方法，其包括基本接触柱的规则阵列和具有低于所采用的光刻技术的最小光刻分辨率F的宽度的发射极接触柱。 在一个实施例中，柱阵列特征具有大约F / 2的尺寸，尽管该尺寸可以减小到与本发明的实施例相容的其它值。 诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。
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