公开(公告)号：US20060286797A1

公开(公告)日：2006-12-21

申请号：US11153747

申请日：2005-06-15

申请人： Fan Zhang ,  Kho Liep ,  Alex See ,  Cheng-Cheh Tou ,  Xiaomei Bu ,  Tae Lee ,  Liang Hsia

发明人： Fan Zhang ,  Kho Liep ,  Alex See ,  Cheng-Cheh Tou ,  Xiaomei Bu ,  Tae Lee ,  Liang Hsia

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76859 ,  H01L21/76856 ,  H01L21/76864

摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.

摘要翻译： 用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。 掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。 在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。 稍后通过平坦化处理去除阻挡层。 在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

公开(公告)号：US20060030128A1

公开(公告)日：2006-02-09

申请号：US10910499

申请日：2004-08-03

申请人： Xiaomei Bu ,  Alex See ,  Tae Lee ,  Fan Zhang ,  Yeon Lim ,  Liang Hsia

发明人： Xiaomei Bu ,  Alex See ,  Tae Lee ,  Fan Zhang ,  Yeon Lim ,  Liang Hsia

IPC分类号： H01L21/78

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

摘要翻译： 一种半导体器件的结构和方法，衬底气隙靠近互连和电介质层。 介电层形成在衬底上的下介电层和下互连之上。 我们在电介质层中形成互连开口。 开口具有介电层的侧壁。 牺牲衬垫形成在互连开口的侧壁上。 形成填充开口的上互连。 我们移除牺牲衬垫/垫片以形成（空气）衬垫间隙。

公开(公告)号：US07989338B2

公开(公告)日：2011-08-02

申请号：US11153747

申请日：2005-06-15

申请人： Fan Zhang ,  Kho Liep Chok ,  Alex See ,  Cheng-Cheh Tan ,  Xiaomei Bu ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Fan Zhang ,  Kho Liep Chok ,  Alex See ,  Cheng-Cheh Tan ,  Xiaomei Bu ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76859 ,  H01L21/76856 ,  H01L21/76864

摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.

摘要翻译： 用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。 掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。 在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。 稍后通过平坦化处理去除阻挡层。 在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

公开(公告)号：US20070293039A1

公开(公告)日：2007-12-20

申请号：US11454397

申请日：2006-06-16

申请人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

摘要翻译： 公开了一种在电介质层中填充间隙的方法。 提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。 形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。 用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。 然后使用ECP来完成间隙的铜填充。 对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

公开(公告)号：US07094669B2

公开(公告)日：2006-08-22

申请号：US10910499

申请日：2004-08-03

申请人： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

公开(公告)号：US07585768B2

公开(公告)日：2009-09-08

申请号：US11454397

申请日：2006-06-16

申请人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/44

CPC分类号： H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

摘要翻译： 公开了一种在电介质层中填充间隙的方法。 提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。 形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。 用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。 然后使用ECP来完成间隙的铜填充。 对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

公开(公告)号：US20060040491A1

公开(公告)日：2006-02-23

申请号：US10923123

申请日：2004-08-21

申请人： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

发明人： Yeow Lim ,  Alex See ,  Tae Lee ,  David Vigar ,  Liang Hsia ,  Kin Pey

IPC分类号： H01L21/4763

CPC分类号： H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

摘要翻译： 用于宽线槽以减少压力的方法和结构。 一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。 通孔插头可以从上方或下方接触宽线。 另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。 宽线有第一个插槽。 第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

公开(公告)号：US20050156269A1

公开(公告)日：2005-07-21

申请号：US11081908

申请日：2005-03-15

申请人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

发明人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L27/095

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US06680239B1

公开(公告)日：2004-01-20

申请号：US09624025

申请日：2000-07-24

申请人： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

发明人： Cher Liang Cha ,  Kok Keng Ong ,  Alex See ,  Lap Chan

IPC分类号： H01L2176

CPC分类号： H01L21/76237

摘要： A method for forming shallow trench isolation (STI) with a higher aspect ratio is given. This method allows the formation of narrower and deeper trench isolation regions while avoiding substrate damage due to excessive etching and severe microloading effects. In addition, it yields uniform depth trenches while avoiding problems of etch residue at the bottom of the trench. This method is achieved by using a process where a trench is etched, and an oxide layer grown along the bottom and sidewalls of the trench. Oxygen or field isolation ions are then implanted into the bottom of the trench. A nitride spacer is then formed along the bottom and sidewalls of the trench, followed by an isotropic etch removing the nitride and oxide from the bottom of the trench. An oxide deposition then fills the trench, followed by a planarization step completing the isolation structure.

摘要翻译： 给出了一种形成具有较高纵横比的浅沟槽隔离（STI）的方法。 该方法允许形成更窄和更深的沟槽隔离区域，同时避免由于过度蚀刻和严重的微负载效应引起的基板损伤。 此外，它产生均匀的深度沟槽，同时避免沟槽底部的蚀刻残留问题。 该方法通过使用其中蚀刻沟槽的工艺和沿着沟槽的底部和侧壁生长的氧化物层来实现。 然后将氧或场隔离离子注入到沟槽的底部。 然后沿着沟槽的底部和侧壁形成氮化物间隔物，随后通过各向同性蚀刻从沟槽的底部去除氮化物和氧化物。 氧化物沉积然后填充沟槽，随后是完成隔离结构的平坦化步骤。

公开(公告)号：US06624489B2

公开(公告)日：2003-09-23

申请号：US10033284

申请日：2001-12-31

申请人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

发明人： Yung Fu Chong ,  Kin Leong Pey ,  Alex See

IPC分类号： H01L2976

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/28052 ,  H01L29/665

摘要： A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.