公开(公告)号：US20080090379A1

公开(公告)日：2008-04-17

申请号：US11955751

申请日：2007-12-13

申请人： Fred Buehrer ,  Anthony Chou ,  Toshiharu Furukawa ,  Renee Mo

发明人： Fred Buehrer ,  Anthony Chou ,  Toshiharu Furukawa ,  Renee Mo

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.

摘要翻译： 一种用于半导体器件的改进的浅沟槽隔离（STI）结构的方法和结构。 STI结构包含STI填充物的氮氧化物顶层。 可选地，STI结构包括邻近硅沟槽壁的STI填充的氮氧化物边缘。 在硅沟槽壁的上边缘附近的氮氧化物边缘的区域包括与氮氧化物边缘的其它区域相比相对较厚并且含有较高浓度的氮的氧氮化物角。 氮氧化物的特征是限制了STI填充高度损失，并且还减少了STI填充物中由于氢氟酸蚀刻和其它制造工艺引起的硅衬底的形成。 限制STI填充高度损失和形成纹理改善了STI结构的功能。 形成STI结构的方法与包括化学机械抛光（CMP）在内的标准半导体器件制造工艺特别兼容，因为该方法包括使用纯二氧化硅STI填充和等离子体和热氮化工艺来形成氧氮化物顶层 和氮氧化物边缘，包括氮氧化物拐角，STI填充。

公开(公告)号：US20060160322A1

公开(公告)日：2006-07-20

申请号：US10905683

申请日：2005-01-17

申请人： Fred Buehrer ,  Anthony Chou ,  Toshiharu Furukawa ,  Renee Mo

发明人： Fred Buehrer ,  Anthony Chou ,  Toshiharu Furukawa ,  Renee Mo

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.

摘要翻译： 一种用于半导体器件的改进的浅沟槽隔离（STI）结构的方法和结构。 STI结构包含STI填充物的氮氧化物顶层。 可选地，STI结构包括邻近硅沟槽壁的STI填充的氮氧化物边缘。 在硅沟槽壁的上边缘附近的氮氧化物边缘的区域包括与氮氧化物边缘的其它区域相比相对较厚并且含有较高浓度的氮的氧氮化物角。 氮氧化物的特征是限制了STI填充高度损失，并且还减少了STI填充物中由于氢氟酸蚀刻和其它制造工艺引起的硅衬底的形成。 限制STI填充高度损失和形成纹理改善了STI结构的功能。 形成STI结构的方法与包括化学机械抛光（CMP）在内的标准半导体器件制造工艺特别兼容，因为该方法包括使用纯二氧化硅STI填充和等离子体和热氮化工艺来形成氧氮化物顶层 和氮氧化物边缘，包括氮氧化物拐角，STI填充。

公开(公告)号：US20110223756A1

公开(公告)日：2011-09-15

申请号：US12721738

申请日：2010-03-11

申请人： James K. Schaeffer ,  Eric D. Luckowski ,  Todd C. Bailey ,  Amy L. Child ,  Daniel Jaeger ,  Renee Mo ,  Ying H. Tsang

发明人： James K. Schaeffer ,  Eric D. Luckowski ,  Todd C. Bailey ,  Amy L. Child ,  Daniel Jaeger ,  Renee Mo ,  Ying H. Tsang

IPC分类号： H01L21/28 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/3105 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66651

摘要： A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

摘要翻译： 描述了一种用于在至少NMOS器件区域中具有稀土氧化物覆盖层（44）的高k栅介质层（32）之上制造金属栅电极（85,86）的方法和装置， 具有无氧等离子体工艺（42）的稀土氧化物覆盖层（44）以改善光致抗蚀剂的粘合性，在稀土氧化物覆盖层（44）上直接形成图案化的光致抗蚀剂层（52），然后施加湿蚀刻工艺 （62）从PMOS器件区域去除所述稀土氧化物覆盖层（44）的暴露部分。

公开(公告)号：US20060057797A1

公开(公告)日：2006-03-16

申请号：US11266855

申请日：2005-11-04

申请人： Atul Ajmera ,  Andres Bryant ,  Percy Gilbert ,  Michael Gribelyuk ,  Edward Maciejewski ,  Renee Mo ,  Shreesh Narasimha

发明人： Atul Ajmera ,  Andres Bryant ,  Percy Gilbert ,  Michael Gribelyuk ,  Edward Maciejewski ,  Renee Mo ,  Shreesh Narasimha

IPC分类号： H01L21/8238

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

公开(公告)号：US20050277263A1

公开(公告)日：2005-12-15

申请号：US10710001

申请日：2004-06-11

申请人： Renee Mo ,  Shreesh Narasimha

发明人： Renee Mo ,  Shreesh Narasimha

IPC分类号： H01L21/331 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76283

摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.

摘要翻译： 通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量 使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

公开(公告)号：US08415212B2

公开(公告)日：2013-04-09

申请号：US12721738

申请日：2010-03-11

申请人： James K. Schaeffer ,  Eric D. Luckowski ,  Todd C. Bailey ,  Amy L. Child ,  Daniel Jaeger ,  Renee Mo ,  Ying H. Tsang

发明人： James K. Schaeffer ,  Eric D. Luckowski ,  Todd C. Bailey ,  Amy L. Child ,  Daniel Jaeger ,  Renee Mo ,  Ying H. Tsang

IPC分类号： H01L21/8238 ,  H01L21/3205

CPC分类号： H01L21/823857 ,  H01L21/28185 ,  H01L21/3105 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66651

摘要： A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

摘要翻译： 描述了一种用于在至少NMOS器件区域中具有稀土氧化物覆盖层（44）的高k栅介质层（32）之上制造金属栅电极（85,86）的方法和装置， 具有无氧等离子体工艺（42）的稀土氧化物覆盖层（44）以改善光致抗蚀剂的粘合性，在稀土氧化物覆盖层（44）上直接形成图案化的光致抗蚀剂层（52），然后施加湿蚀刻工艺 （62）从PMOS器件区域去除所述稀土氧化物覆盖层（44）的暴露部分。

公开(公告)号：US20060022270A1

公开(公告)日：2006-02-02

申请号：US10710736

申请日：2004-07-30

申请人： Diane Boyd ,  Judson Holt ,  MeiKei Ieong ,  Renee Mo ,  Zhibin Ren ,  Ghavam Shahidi

发明人： Diane Boyd ,  Judson Holt ,  MeiKei Ieong ,  Renee Mo ,  Zhibin Ren ,  Ghavam Shahidi

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.

摘要翻译： 超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。 掩埋氧化层。 使SOI层变薄以形成超薄SOI层。 形成将SOI层分离成N和P接地平面区域的隔离沟槽。 用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。 在N和P接地平面区域之上形成半导体沟道区。 在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。 可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

公开(公告)号：US20060022266A1

公开(公告)日：2006-02-02

申请号：US10710738

申请日：2004-07-30

申请人： Brian Messenger ,  Renee Mo ,  Dominic Schepis

发明人： Brian Messenger ,  Renee Mo ,  Dominic Schepis

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.

摘要翻译： 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂的半导体衬底的表面上形成包含氧和碳的单层; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层用作可以随后形成源/漏扩散区的凸起层。

公开(公告)号：US20070254479A1

公开(公告)日：2007-11-01

申请号：US11415922

申请日：2006-05-01

申请人： Sunfei Fang ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee Mo ,  Balasubramanian Pranatharthiharan ,  Jay Strane

发明人： Sunfei Fang ,  Randolph Knarr ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Renee Mo ,  Balasubramanian Pranatharthiharan ,  Jay Strane

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

摘要： The present invention relates to a method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region. Preferably, each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region is essentially free of metal and metal silicide. More preferably, the method comprises the steps of nickel or nickel alloy deposition, low-temperature annealing, nickel etching, high-temperature annealing, and aqua regia etching.

摘要翻译： 本发明涉及一种用于在由暴露的电介质区彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 优选地，如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的至少硅化镍和铂硅化物，并且暴露的电介质区域基本上不含金属和金属硅化物。 更优选地，该方法包括镍或镍合金沉积，低温退火，镍蚀刻，高温退火和王水腐蚀的步骤。

公开(公告)号：US20060055393A1

公开(公告)日：2006-03-16

申请号：US10942303

申请日：2004-09-16

申请人： Bachir Dirahoui ,  Renee Mo ,  Ravikumar Ramachandran ,  Eric Solecky

发明人： Bachir Dirahoui ,  Renee Mo ,  Ravikumar Ramachandran ,  Eric Solecky

IPC分类号： G01R19/00

CPC分类号： H01L22/12

摘要： A process implementing steps for determining encroachment of a spacer structure in a semiconductor device having thick and thin spacer regions, including a transition region formed therebetween. The method steps comprise: obtaining a line width roughness (LWR) measurement at at least one location along each thick, thin and transition spacer regions; determining a threshold LWR measurement value based on the LWR measurements; defining a region of interest (ROI) and obtaining a further LWR measurement in the ROI; comparing the LWR measurement in the ROI against the threshold LWR measurement value; and, notifying a user that either encroachment of the spacer structure is present when the LWR measurement in the ROI is below the threshold LWR measurement value, or that no encroachment of the spacer structure is present when the LWR measurement in the ROI is above the threshold LWR measurement value.

摘要翻译： 一种实现用于确定具有厚而薄的间隔区域的半导体器件中间隔结构的侵入的步骤的方法，包括在它们之间形成的过渡区域。 方法步骤包括：在沿着每个厚的，薄的和过渡间隔区的至少一个位置处获得线宽粗糙度（LWR）测量; 基于LWR测量确定阈值LWR测量值; 定义感兴趣区域（ROI）并在ROI中获得进一步的LWR测量; 将ROI中的LWR测量值与阈值LWR测量值进行比较; 并且当ROI中的LWR测量低于阈值LWR测量值时或者当ROI中的LWR测量高于阈值时不通知间隔物结构的侵入，通知用户是否存在间隔结构的侵入 LWR测量值。