公开(公告)号：US09377543B2

公开(公告)日：2016-06-28

申请号：US14687489

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jin Cai ,  Tak H. Ning ,  Jeng-Bang Yau ,  Sufi Zafar

IPC: G01T1/20 ,  G01T1/24 ,  H01L31/115 ,  H01L27/14 ,  H01L31/11 ,  G01T3/08 ,  G01N27/403 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/118 ,  H01L27/146

CPC classification number: G01T1/247 ,  G01N27/403 ,  G01T3/08 ,  H01L27/14 ,  H01L27/14681 ,  H01L31/022408 ,  H01L31/035272 ,  H01L31/1105 ,  H01L31/115 ,  H01L31/118

Abstract: A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

公开(公告)号：US20160035743A1

公开(公告)日：2016-02-04

申请号：US14866878

申请日：2015-09-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L27/12 ,  H01L29/417 ,  H01L25/065 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L25/065 ,  H01L27/092 ,  H01L29/41783 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

公开(公告)号：US09548238B2

公开(公告)日：2017-01-17

申请号：US13964286

申请日：2013-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-Lin Cheng ,  Jack O. Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76808 ,  H01L21/76895 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device, comprises forming an organic planarization layer on a plurality of gates on a substrate, wherein the plurality of gates each include a spacer layer thereon, forming an oxide layer on the organic planarization layer, removing a portion of the oxide layer to expose the organic planarization layer, stripping the organic planarization layer to form a cavity, patterning a direct lithographically-patternable gap dielectric on at least one of the gates in the cavity, and depositing a conductive contact in a remaining portion of the cavity.

Abstract translation: 一种半导体器件的制造方法，包括在基板上的多个栅极上形成有机平坦化层，其中，所述多个栅极各自包括间隔层，在所述有机平坦化层上形成氧化物层， 氧化层以暴露有机平坦化层，剥离有机平坦化层以形成空腔，在空腔中的至少一个栅极上图案化直接可光刻图案化的间隙电介质，以及在空腔的剩余部分中沉积导电接触 。

公开(公告)号：US09385122B2

公开(公告)日：2016-07-05

申请号：US14686260

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Szu-Lin Cheng ,  Jack Oon Chu ,  Isaac Lauer ,  Jeng-Bang Yau

IPC: H01L29/76 ,  H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/267 ,  H01L29/165

CPC classification number: H01L27/088 ,  H01L21/02647 ,  H01L21/3065 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device comprises growing a source/drain epitaxy region over a plurality of gates on a substrate, wherein a top surface of the source/drain epitaxy region is at a height above a top surface of each of the plurality of gates, forming at least one opening in the source/drain epitaxy region over a top surface of at least one gate, forming a silicide layer on the source/drain epitaxy region, wherein the silicide layer lines lateral sides of the at least one opening, depositing a dielectric layer on the silicide layer, wherein the dielectric layer is deposited in the at least one opening between the silicide layer on lateral sides of the at least one opening, etching the dielectric layer to form a contact area, and depositing a conductor in the contact area.