公开(公告)号：US20170229443A1

公开(公告)日：2017-08-10

申请号：US15497924

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, JR. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/78 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

公开(公告)号：US20160379972A1

公开(公告)日：2016-12-29

申请号：US15140516

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, JR. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

Abstract translation: 场效应二极管结构使用横截面为L形的接合结构（从平面部分延伸的翅片）。 阳极位于翅片的顶面，阴极位于平面部分的端面。 翅片和平面部分的垂直度导致阳极和阴极彼此垂直。 第一栅极绝缘体在顶表面和平面部分之间接触翅片。 第一栅极导体接触第一栅极绝缘体，并且第一栅极绝缘体位于第一栅极导体和鳍的表面之间。 另外，第二栅极绝缘体接触端面和鳍之间的平面部分。 第二栅极导体与第二栅极绝缘体接触，第二栅极绝缘体位于第二栅极导体与平面部分的表面之间。

公开(公告)号：US20170236917A1

公开(公告)日：2017-08-17

申请号：US15044431

申请日：2016-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Andreas Scholze

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

公开(公告)号：US09704852B2

公开(公告)日：2017-07-11

申请号：US15140516

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L29/66 ,  H01L29/15 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

公开(公告)号：US09601513B1

公开(公告)日：2017-03-21

申请号：US14977899

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Terence B. Hook ,  Andreas Scholze ,  Lars W. Liebmann ,  Roger A. Quon ,  Andrew H. Simon

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/84 ,  H01L21/845 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/535 ,  H01L29/0649

Abstract: Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.

公开(公告)号：US10297589B2

公开(公告)日：2019-05-21

申请号：US15497924

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert J. Gauthier, Jr. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

公开(公告)号：US09786765B2

公开(公告)日：2017-10-10

申请号：US15044431

申请日：2016-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Andreas Scholze

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

公开(公告)号：US09536882B2

公开(公告)日：2017-01-03

申请号：US14574504

申请日：2014-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Robert R. Robison ,  Andreas Scholze

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1087

Abstract: Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

Abstract translation: 公开了用于散装FinFET的隔离技术。 半导体器件包括在半导体衬底上具有翅片结构的半导体衬底。 翅片结构垂直于半导体衬底并具有上部和下部。 源极和漏极区域与翅片结构相邻。 栅极结构围绕鳍结构的上部。 在半导体衬底中提供良好的接触点。 翅片结构的下部包括在被栅极结构包围的区域和半导体衬底之间的子鳍。 子鳍直接接触半导体衬底。 翅片结构的上部和副翅片的上部是未掺杂的。 子鳍片的下部可以被掺杂。 从阱接触点施加到副散热片的下部的电势减小了从翅片结构的上部的泄漏电流。