公开(公告)号：US09312145B2

公开(公告)日：2016-04-12

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L21/469 ,  H01L21/324 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。

公开(公告)号：US09202697B2

公开(公告)日：2015-12-01

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying Luo ,  Feng Zhou ,  Yan Ping Shen ,  Haiting Wang ,  Haoran Shi ,  Wei Hua Tong ,  Seung Kim ,  Yong Meng Lee

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。

公开(公告)号：US20150294915A1

公开(公告)日：2015-10-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09698269B2

公开(公告)日：2017-07-04

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua Tong ,  Tien-Ying Luo ,  Yan Ping Shen ,  Feng Zhou ,  Jun Lian ,  Haoran Shi ,  Min-hwa Chi ,  Jin Ping Liu ,  Haiting Wang ,  Seung Kim

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/324 ,  H01L21/02 ,  H01L21/321 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US09287180B2

公开(公告)日：2016-03-15

申请号：US14749245

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a first fin structure overlying a first type region in a semiconductor substrate and forming a second fin structure overlying a second type region in the semiconductor substrate. A gate is formed overlying each fin structure and defines a channel region in each fin structure. The method includes masking the second type region and etching the first fin structure around the gate in the first fin structure to expose the channel region in the first fin structure. Further, the method includes doping the channel region in the first fin structure, and forming source/drain regions of the first fin structure around the channel region in the first fin structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：形成覆盖半导体衬底中的第一类型区域的第一鳍结构，并形成覆盖半导体衬底中第二类型区域的第二鳍结构。 形成在每个鳍结构上方的栅极，并且限定每个鳍结构中的沟道区。 该方法包括掩蔽第二类型区域并蚀刻第一鳍结构中的栅极周围的第一鳍结构以暴露第一鳍结构中的沟道区。 此外，该方法包括在第一鳍结构中掺杂沟道区，并且在第一鳍结构中的沟道区周围形成第一鳍结构的源/漏区。

公开(公告)号：US09093476B2

公开(公告)日：2015-07-28

申请号：US13954289

申请日：2013-07-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jinping Liu ,  Bharat Krishnan ,  Bongki Lee ,  Vidmantas Sargunas ,  Weihua Tong ,  Seung Kim

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US09087870B2

公开(公告)日：2015-07-21

申请号：US13904626

申请日：2013-05-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Huang Liu ,  HongLiang Shen ,  Jin Ping Liu ,  Seung Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/3115 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括蚀刻设置在两个相邻散热片之间的STI沟槽中的增强的高纵横比工艺（eHARP）氧化物填充物，以形成凹陷的eHARP氧化物填充物。 两个相邻的翅片从体半导体衬底延伸。 覆盖凹陷的eHARP氧化物填充物形成硅层。 将硅层转化为热氧化物层，以进一步用氧化物材料填充STI沟槽。

公开(公告)号：US20140353795A1

公开(公告)日：2014-12-04

申请号：US13904626

申请日：2013-05-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Huang Liu ,  HongLiang Shen ,  Jin Ping Liu ,  Seung Kim

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括蚀刻设置在两个相邻散热片之间的STI沟槽中的增强的高纵横比工艺（eHARP）氧化物填充物，以形成凹陷的eHARP氧化物填充物。 两个相邻的翅片从体半导体衬底延伸。 覆盖凹陷的eHARP氧化物填充物形成硅层。 将硅层转化为热氧化物层，以进一步用氧化物材料填充STI沟槽。

公开(公告)号：US08722485B1

公开(公告)日：2014-05-13

申请号：US13851810

申请日：2013-03-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Yiqun Liu ,  Tae-Hoon Kim ,  Seung Kim ,  Haiting Wang ,  Huang Liu

IPC: H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28167 ,  H01L21/823857 ,  H01L29/78

Abstract: A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate having formed thereon a sacrificial silicon oxide layer, an interlayer dielectric layer formed over the sacrificial silicon oxide layer, and a dummy gate structure formed over the sacrificial silicon oxide layer and within the interlayer dielectric layer, removing the dummy gate structure to form an opening within the interlayer dielectric layer, and removing the sacrificial silicon oxide layer within the opening to expose the semiconductor substrate within the opening. The method further includes the steps of thermally forming an oxide layer on the exposed semiconductor substrate within the opening, subjecting the thermally formed oxide layer to a decoupled plasma oxidation treatment, and etching the thermally formed oxide layer using a self-saturated wet etch chemistry. Still further, the method includes depositing a high-k dielectric over the thermally formed oxide layer within the opening.

Abstract translation: 一种制造集成电路的方法包括以下步骤：提供其上形成有牺牲氧化硅层的半导体衬底，形成在牺牲氧化硅层上的层间电介质层，以及在牺牲氧化硅层上形成的虚拟栅极结构， 所述层间介电层，去除所述虚拟栅极结构以在所述层间电介质层内形成开口，以及去除所述开口内的所述牺牲氧化硅层以在所述开口内露出所述半导体衬底。 该方法还包括以下步骤：在开口内的暴露的半导体衬底上热氧化形成氧化物层，对热形成的氧化物层进行去耦等离子体氧化处理，以及使用自饱和的湿蚀刻化学法蚀刻热成型的氧化物层。 此外，该方法包括在开口内的热形成的氧化物层上沉积高k电介质。