公开(公告)号：US09511474B2

公开(公告)日：2016-12-06

申请号：US15005029

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wei Lu ,  Alex See

IPC: B24B49/00 ,  B24B37/005 ,  B24B37/32

CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在台板上的抛光垫; 用于将晶片保持在抛光垫上的头组件，其中所述头组件包括所述保持环; 用于感测保持环和其膜之间的台阶高度的传感器以及用于基于保持环与其膜之间的台阶高度来调整保持环的移动的控制器，以确保台阶高度保持在固定值作为保持 戒指磨损了。

公开(公告)号：US20160351507A1

公开(公告)日：2016-12-01

申请号：US14721121

申请日：2015-05-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shijie Wang ,  Yong Feng Fu ,  Siew Yong Leong ,  Lei Wang ,  Alex See

IPC: H01L23/544 ,  H01L21/3105

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F7/70683 ,  H01L21/3105

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a base dielectric layer, a first dielectric layer overlying the base dielectric layer, and a second dielectric layer overlying the first dielectric layer. A first overlay mark is positioned within the first dielectric layer, and a second overlay mark is positioned within the second dielectric layer, where the second overlay mark is offset from the first overlay mark. First and second blocks are positioned within the base dielectric layer, where the first overlay mark directly overlays the first block and the second overlay mark directly overlays the second block.

Abstract translation: 提供了集成电路及其制造方法。 集成电路包括基底电介质层，覆盖在基底电介质层上的第一电介质层和覆盖在第一电介质层上的第二电介质层。 第一覆盖标记位于第一介电层内，并且第二覆盖标记位于第二介电层内，其中第二覆盖标记偏离第一覆盖标记。 第一和第二块位于基底介电层内，其中第一覆盖标记直接覆盖第一块，而第二覆盖标记直接覆盖第二块。

公开(公告)号：US20160133524A1

公开(公告)日：2016-05-12

申请号：US14538850

申请日：2014-11-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Liang Li ,  Wei Lu ,  Lian Choo Goh ,  Yung Fu Alfred Chong ,  Fangyue Liu ,  Alex See

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/266 ,  H01L21/265

CPC classification number: H01L21/823462 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493

Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

Abstract translation: 提供了制造具有改进的有源区的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有上表面的半导体衬底，并且包括形成在低电压器件区域和高压器件区域中的有源区和隔离区。 该方法包括在隔离区域和高压设备区域中的有源区域之间选择性地形成空隙以暴露有源侧表面。 该方法还包括氧化上表面和活性侧表面以在低电压器件区域和高电压器件区域上形成栅氧化层。

公开(公告)号：US09202746B2

公开(公告)日：2015-12-01

申请号：US14145581

申请日：2013-12-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lei Wang ,  Lup San Leong ,  Wei Lu ,  Alex See

IPC: H01L21/3205 ,  H01L29/78 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522

CPC classification number: H01L21/76819 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/76805 ,  H01L21/76837 ,  H01L21/76879 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with reduced shorting and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing a gap fill dielectric overlying a semiconductor substrate. The gap fill dielectric is formed with an upper surface having a height differential. The method includes reducing the height differential of the upper surface of the gap fill dielectric. Further, the method includes depositing an interlayer dielectric overlying the gap fill dielectric. Also, the method forms an electrical contact to a selected location overlying the semiconductor substrate.

Abstract translation: 提供具有减少短路的集成电路和制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括沉积覆盖半导体衬底的间隙填充电介质。 间隙填充电介质形成有具有高度差的上表面。 该方法包括减小间隙填充电介质的上表面的高度差。 此外，该方法包括沉积覆盖间隙填充电介质的层间电介质。 此外，该方法形成与覆盖半导体衬底的选定位置的电接触。

公开(公告)号：US20150311221A1

公开(公告)日：2015-10-29

申请号：US14259460

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jingyan Huang ,  Chuan Wang ,  Chim Seng Seet ,  Yun Ling Tan ,  Alex See

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/45 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L29/49 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66825

Abstract: Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material.

Abstract translation: 提供了具有硅化镍触点的集成电路和用于制造具有硅化镍触点的集成电路的方法。 用于制造集成电路的示例性方法包括提供半导体衬底并在半导体衬底上形成非易失性存储器结构。 非易失性存储器结构包括栅极表面。 该方法还包括在栅极表面上沉积含镍材料。 此外，该方法包括对非易失性存储器结构进行退火并在含镍材料的栅极表面上形成硅化镍接触。

公开(公告)号：US09627219B2

公开(公告)日：2017-04-18

申请号：US14253874

申请日：2014-04-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/31055 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/76256

Abstract: Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.

公开(公告)号：US09620418B2

公开(公告)日：2017-04-11

申请号：US14538850

申请日：2014-11-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Liang Li ,  Wei Lu ,  Lian Choo Goh ,  Yung Fu Alfred Chong ,  Fangyue Liu ,  Alex See

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311

CPC classification number: H01L21/823462 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493

Abstract: Methods for fabricating integrated circuits having improved active regions are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having an upper surface and including active regions and isolation regions formed in a low voltage device area and in a high voltage device area. The method includes selectively forming voids between the isolation regions and the active regions in the high voltage device area to expose active side surfaces. The method further includes oxidizing the upper surface and the active side surfaces to form a gate oxide layer over the low voltage device area and the high voltage device area.

公开(公告)号：US20160284991A1

公开(公告)日：2016-09-29

申请号：US14665013

申请日：2015-03-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Zheng Zou ,  Alex See ,  Shyue Seng Tan

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/06 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1675

Abstract: Integrated circuits and methods for manufacturing the same are provided. An integrated circuit includes a lower electrode overlying a substrate, an insulating layer overlying the lower electrode, and an upper electrode overlying the insulating layer. The lower electrode, the insulating layer, and the upper electrode form a stack having a side surface. A phase change spacer is adjacent to the side surface, where the phase change spacer is electrically connected to the lower electrode and the upper electrode.

Abstract translation: 提供了集成电路及其制造方法。 集成电路包括覆盖基板的下电极，覆盖在下电极上的绝缘层和覆盖绝缘层的上电极。 下电极，绝缘层和上电极形成具有侧表面的叠层。 相变间隔件与侧表面相邻，其中相变间隔件电连接到下电极和上电极。

公开(公告)号：US09242338B2

公开(公告)日：2016-01-26

申请号：US14059448

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Lei Wang ,  Xuesong Rao ,  Wei Lu ,  Alex See

IPC: B24B49/16 ,  B24B37/005 ,  B24B37/32

CPC classification number: B24B37/005 ,  B24B37/32 ,  B24B49/16

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在压板台上的抛光垫，用于将晶片保持在抛光垫上的头组件，其中头部组件包括保持环，用于感测保持环上的凹槽的深度的传感器，以及用于确定 基于槽的深度更新施加到保持环的压力，并且在处理期间将更新的压力施加到保持环。

公开(公告)号：US09023725B2

公开(公告)日：2015-05-05

申请号：US13720933

申请日：2012-12-19

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kwee Liang Yeo ,  Chim Seng Seet ,  Zheng Zou ,  Alex See

IPC: H01L21/3205 ,  H01L29/78 ,  H01L29/40 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/28052 ,  H01L29/401 ,  H01L29/665 ,  H01L29/66545

Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate. A gate having a gate electrode and sidewall spacers are formed adjacent to sidewalls of the gate. A height HG of the gate is lower than a height HS of the sidewall spacers. A metal or metal alloy layer is deposited over the spacers, gate and the substrate. The substrate is processed to form metal silicide contact at least over the gate electrode. A top surface of the metal silicide contact over the gate electrode is about coplanar with a top of the sidewall spacer, and the difference between the height of the gate and spacers prevent formation of metal silicide filaments on top of the sidewall spacers.

Abstract translation: 公开了一种用于形成装置的装置和方法。 该方法包括提供基板。 具有栅电极和侧壁间隔物的栅极邻近栅极的侧壁形成。 栅极的高度HG低于侧壁间隔物的高度HS。 金属或金属合金层沉积在间隔物，栅极和基底上。 至少在栅电极上处理衬底以形成金属硅化物接触。 栅电极上的金属硅化物接触的顶表面与侧壁间隔物的顶部大致共面，并且栅极和间隔物的高度之间的差异阻止了在侧壁间隔物的顶部上形成金属硅化物细丝。