利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.039 秒)

    Method of manufacturing a semiconductor device
    1.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08853052B2

    公开(公告)日：2014-10-07

    申请号：US13204352

    申请日：2011-08-05

    申请人： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

    发明人： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

    IPC分类号： H01L21/76 ,  H01L29/00 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

    摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

    摘要翻译： 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

    Method of Manufacturing a Semiconductor Device
    2.
    发明申请
    Method of Manufacturing a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20130034948A1

    公开(公告)日：2013-02-07

    申请号：US13204352

    申请日：2011-08-05

    申请人： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

    发明人： Gin-Chen Huang ,  Yi-An Lin ,  Ching-Hong Jiang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/31055

    摘要： A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.

    摘要翻译： 公开了一种制造半导体器件的方法。 一种示例性方法包括提供衬底。 在半导体衬底上形成电介质层，并在电介质层上形成阻挡层。 阻挡层和电介质层包括不同的材料。 该方法还包括在停止层上形成图案化的硬掩模层，并通过图案化的硬掩模层蚀刻半导体衬底以形成多个沟槽。 该方法还包括在半导体衬底上沉积隔离材料并基本上填充多个沟槽。 此后，在半导体衬底上执行CMP处理，其中CMP处理在停止层上停止。

    Method of protecting an interlayer dielectric layer and structure formed thereby
    5.
    发明授权
    Method of protecting an interlayer dielectric layer and structure formed thereby 有权
    保护层间电介质层的方法和由此形成的结构

    公开(公告)号：US09263252B2

    公开(公告)日：2016-02-16

    申请号：US13735949

    申请日：2013-01-07

    申请人： Chun-Wei Chang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann ,  Yu-Lien Huang

    发明人： Chun-Wei Chang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann ,  Yu-Lien Huang

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/02 ,  H01L29/66

    CPC分类号： H01L21/022 ,  H01L29/66545

    摘要： This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.

    摘要翻译： 该描述涉及包括在衬底上形成层间电介质（ILD）层和虚拟栅极结构并在ILD层的顶部形成腔的方法。 该方法还包括形成保护层以填充空腔。 该方法还包括平坦化保护层。 平坦化保护层的顶表面与虚拟栅结构的顶表面平齐。 该描述还涉及包括第一和第二栅极结构以及形成在衬底上的ILD层的半导体器件。 半导体器件还包括形成在ILD层上的保护层，保护层具有与ILD层不同的蚀刻选择性，其中保护层的顶表面与第一和第二栅极结构的顶表面平齐。

    IN-SITU SPECTROMETRY
    7.
    发明申请
    IN-SITU SPECTROMETRY 审中-公开
    现场光谱

    公开(公告)号：US20120009690A1

    公开(公告)日：2012-01-12

    申请号：US12834617

    申请日：2010-07-12

    申请人： Clement Hsingjen Wann ,  Hung-Ming Chen ,  Chang-Yun Chang ,  Sey-Ping Sun

    发明人： Clement Hsingjen Wann ,  Hung-Ming Chen ,  Chang-Yun Chang ,  Sey-Ping Sun

    IPC分类号： H01L21/66 ,  B08B3/04

    CPC分类号： H01L21/67075 ,  H01L21/67276 ,  H01L22/12

    摘要： The present disclosure provides a system for in-situ spectrometry. The system includes a wafer-cleaning machine that cleans a surface of a semiconductor wafer using a cleaning solution. The system also includes a spectrometry machine that is coupled to the wafer-cleaning machine. The spectrometry machine receives a portion of the cleaning solution from the wafer-cleaning machine. The portion of the cleaning solution collects particles from the wafer during the cleaning. The spectrometry machine is operable to analyze a particle composition of a portion of the wafer based on the portion of the cleaning solution, while the wafer remains in the wafer-cleaning machine during the particle composition analysis.

    摘要翻译： 本公开提供了一种用于原位光谱法的系统。 该系统包括使用清洁溶液清洁半导体晶片的表面的晶片清洁机。 该系统还包括耦合到晶片清洁机的光谱测定机。 光谱测定机从晶片清洁机接收清洁溶液的一部分。 在清洁期间，清洁溶液的一部分从晶片收集颗粒。 光谱测定仪可操作以基于清洁溶液的一部分分析晶片的一部分的颗粒组成，同时在颗粒组成分析期间晶片保留在晶片清洁机中。

    Semiconductor devices with active semiconductor height variation
    8.
    发明授权
    Semiconductor devices with active semiconductor height variation 有权
    具有半导体高度变化的半导体器件

    公开(公告)号：US08497556B2

    公开(公告)日：2013-07-30

    申请号：US13607023

    申请日：2012-09-07

    申请人： David E. Brown ,  Hans Van Meer ,  Sey-Ping Sun

    发明人： David E. Brown ,  Hans Van Meer ,  Sey-Ping Sun

    IPC分类号： H01L31/119

    CPC分类号： H01L29/0684 ,  H01L21/84 ,  H01L27/1203

    摘要： A semiconductor product has different active thicknesses of silicon on a single semiconductor substrate. The thickness of the silicon layer is changed either by selectively adding silicon or subtracting silicon from an original layer of silicon. The different active thicknesses are suitable for use in different types of devices, such as diodes and transistors.

    摘要翻译： 半导体产品在单个半导体衬底上具有不同的有源厚度的硅。 通过选择性地添加硅或从原始硅层减去硅来改变硅层的厚度。 不同的有源厚度适用于不同类型的器件，例如二极管和晶体管。

    Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
    9.
    发明授权
    Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility 有权
    基于具有高应力衬垫的Si-Ge的半导体器件，用于增强通道载流子迁移率

    公开(公告)号：US07053400B2

    公开(公告)日：2006-05-30

    申请号：US10838330

    申请日：2004-05-05

    申请人： Sey-Ping Sun ,  David E. Brown

    发明人： Sey-Ping Sun ,  David E. Brown

    IPC分类号： H01L31/072

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

    摘要： The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.

    摘要翻译： Si-Ge器件的晶体管沟道区域中的载流子迁移率通过使用应力衬里而增加。 实施例包括施加覆盖松弛的源极/漏极区域的高压缩或拉伸应力膜。 其他实施例包括分别在栅极电极和P沟道或N沟道晶体管的应变Si源极/漏极区之后施加高度压缩或高拉伸应力膜，在硅化物间隔物去除之后。

    Self-aligning silicon oxynitride stack for improved isolation structure
    10.
    发明授权
    Self-aligning silicon oxynitride stack for improved isolation structure 有权
    自对准硅氮氧化物叠层，用于改善隔离结构

    公开(公告)号：US06265283B1

    公开(公告)日：2001-07-24

    申请号：US09373217

    申请日：1999-08-12

    申请人： Homi E. Nariman ,  Sey-Ping Sun ,  H. Jim Fulford

    发明人： Homi E. Nariman ,  Sey-Ping Sun ,  H. Jim Fulford

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.

    摘要翻译： 提供了在基板上制造隔离结构的方法。 一方面，提供一种在衬底上制造隔离结构的方法，包括在衬底上形成第一绝缘层，其中第一绝缘层具有第一侧壁。 在具有第二侧壁的基板中形成沟槽。 在沟槽中形成第二绝缘层。 第二绝缘层横向移动第二侧壁。 通过加热使第一绝缘层致密化，从而释放出气体，从而使第一侧壁与第二侧壁大致垂直对准。 由于沟槽隔离结构回缩引起的基底侵蚀的风险降低。 沟槽边缘被厚的隔离材料覆盖。