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    Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same
    5.
    发明授权
    Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same 有权
    具有改善SiCOH电介质界面强度的结构及其制备方法

    公开(公告)号：US07067437B2

    公开(公告)日：2006-06-27

    申请号：US10662022

    申请日：2003-09-12

    申请人： Daniel C. Edelstein ,  Alfred Grill ,  Vishnubhai V. Patel ,  Darryl D. Restaino

    发明人： Daniel C. Edelstein ,  Alfred Grill ,  Vishnubhai V. Patel ,  Darryl D. Restaino

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/3122 ,  H01L21/31633 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

    摘要： A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.

    摘要翻译： 半导体器件结构和制造方法包括具有顶部第一层的衬底; 位于所述第一层顶部的第二薄过渡层; 以及位于所述过渡层顶部的第三层，其中所述第二薄过渡层在所述结构的所述第一和第三层之间提供强粘合力和内聚强度。 此外，半导体器件结构和制造方法包括绝缘结构，其包括多个介电层和导电层，其中设置有各自的过渡键合层以增强不同层之间的界面强度。 此外，电子器件结构包括绝缘和导电材料层，作为后端线（“BEOL”）布线结构中的层间或层间电介质，其中不同对的介电膜之间的界面强度由 薄的中间过渡粘合层。

    Enhanced T-gate structure for modulation doped field effect transistors
    9.
    发明授权
    Enhanced T-gate structure for modulation doped field effect transistors 有权
    用于调制掺杂场效应晶体管的增强型T栅极结构

    公开(公告)号：US06972440B2

    公开(公告)日：2005-12-06

    申请号：US10750697

    申请日：2004-01-02

    申请人： Dinkar Singh ,  Katherine Lynn Saenger ,  Vishnubhai V. Patel ,  Alfred Grill ,  Steven John Koester

    发明人： Dinkar Singh ,  Katherine Lynn Saenger ,  Vishnubhai V. Patel ,  Alfred Grill ,  Steven John Koester

    IPC分类号： H01L21/285 ,  H01L29/423 ,  H01L31/0328

    CPC分类号： H01L21/28587 ,  H01L29/42316

    摘要： A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

    摘要翻译： 公开了用于调制掺杂场效应晶体管（MODFET）的增强型T栅极的结构和方法。 增强型T型栅极具有夹持T型栅极颈部的绝缘体隔离层。 间隔层比T形杆部分突出部薄。 绝缘层提供机械支撑并保护T型门的易损颈部在后续装置处理过程中不会发生化学侵蚀，从而使T型门结构具有高度的可伸缩性并提高产量。 使用薄的共形低介电常数绝缘层确保低的寄生栅极电容，并且当源极到栅极间隔减小到更小的尺寸时，可以降低栅极和源极冶金的短路的风险。