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    Dual cap layer in damascene interconnection processes
    2.
    发明授权
    Dual cap layer in damascene interconnection processes 有权
    大马士革互连工艺中的双盖层

    公开(公告)号：US07129162B2

    公开(公告)日：2006-10-31

    申请号：US10429119

    申请日：2003-05-02

    申请人： Hyesook Hong ,  Guoqiang Xing ,  Ping Jiang

    发明人： Hyesook Hong ,  Guoqiang Xing ,  Ping Jiang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76808

    摘要： Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.

    摘要翻译： 公开了用于形成铜导体（30,130）的镶嵌方法。 根据所公开的方法，在将通孔或沟槽蚀刻到下面的导体（12;）之前，在有机硅酸盐玻璃绝缘层（16; 116,120）上形成双重覆盖层（18,20; 122,124）。 112）。 双盖层包括碳化硅层（18; 124）和氮化硅层（20; 122）。 碳化硅层（18; 124）和氮化硅层（20; 122）可以以相对于彼此的任何顺序沉积。 碳化硅层（18; 124）在蚀刻通过绝缘层（16; 116,120）时保持通孔或沟槽的临界尺寸，而氮化硅层（20; 122）抑制抗蚀剂的失效机理 中毒 该方法适用于单镶嵌工艺，但也可用于双镶嵌铜工艺。

    Damascene cap layer process for integrated circuit interconnects
    4.
    发明授权
    Damascene cap layer process for integrated circuit interconnects 有权
    用于集成电路互连的镶嵌帽层工艺

    公开(公告)号：US06410426B1

    公开(公告)日：2002-06-25

    申请号：US09901392

    申请日：2001-07-09

    申请人： Guoqiang Xing ,  Ping Jiang

    发明人： Guoqiang Xing ,  Ping Jiang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/76802 ,  Y10S438/97

    摘要： The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).

    摘要翻译： 本发明描述了一种用于形成集成电路互连的方法。 在低k电介质层（40）上形成覆盖层（50）。 蚀刻覆盖层（50）和低k电介质层（40）以在填充有导电材料（90）（95）的低k电介质（4）中形成通孔和/或沟槽。

    Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
    5.
    发明授权
    Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities 有权
    用于形成单镶嵌通孔或沟槽的方法以及通过空腔形成双镶嵌

    公开(公告)号：US07214609B2

    公开(公告)日：2007-05-08

    申请号：US10313491

    申请日：2002-12-05

    申请人： Ping Jiang ,  Rob Kraft ,  Guoqiang Xing ,  Karen H. R. Kirmse ,  Eden Zielinski

    发明人： Ping Jiang ,  Rob Kraft ,  Guoqiang Xing ,  Karen H. R. Kirmse ,  Eden Zielinski

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/76802

    摘要： Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.

    摘要翻译： 公开了用于在单个镶嵌互连结构中形成沟槽或通孔腔的方法，包括蚀刻介电层以在其中形成空腔并暴露下面的蚀刻停止层，以及蚀刻暴露的蚀刻停止层以延伸空腔，并且 暴露现有互连结构中的导电特征，其中蚀刻介电层的一部分并蚀刻蚀刻停止层的暴露部分同时进行，其间基本上没有中间处理步骤。 还公开了在双镶嵌互连结构中形成通孔腔的方法，包括在现有互连结构上形成蚀刻停止层，在蚀刻停止层上形成电介质层，蚀刻介电层的一部分以形成 并且暴露蚀刻停止层的一部分，以及蚀刻蚀刻停止层以延伸通孔腔，其中介电层在蚀刻停止层的蚀刻期间被覆盖。

    Hydrogen-free contact etch for ferroelectric capacitor formation
    8.
    发明授权
    Hydrogen-free contact etch for ferroelectric capacitor formation 有权
    用于铁电电容器形成的无氢接触蚀刻

    公开(公告)号：US06485988B2

    公开(公告)日：2002-11-26

    申请号：US09741650

    申请日：2000-12-19

    申请人： Shawming Ma ,  Guoqiang Xing ,  Rahim Kavari ,  Scott R. Summerfelt ,  Tomoyuki Sakoda

    发明人： Shawming Ma ,  Guoqiang Xing ,  Rahim Kavari ,  Scott R. Summerfelt ,  Tomoyuki Sakoda

    IPC分类号： H01L2100

    CPC分类号： H01L21/31122 ,  H01L21/32136 ,  H01L21/76838 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60

    摘要： An embodiment of the instant invention is a method of forming a conductive contact to a top electrode (308 and 310 of FIG. 4d) of a ferroelectric capacitor comprised of a bottom electrode (304 of FIG. 4d) situated under the top electrode and a ferroelectric material (306 of FIG. 4d) situated between the top electrode and the bottom electrode, the method comprising the steps of: forming a layer (408 or 312 of FIG. 4) over the top electrode; forming an opening (414 of FIG. 4d) in the layer to expose a portion of the top electrode by etching the opening into the layer using a hydrogen-free etchant; and depositing conductive material (432 of FIG. 4d) in the opening to form an electrical connection with the top electrode.

    摘要翻译： 本发明的一个实施方案是一种形成导电接触的方法，该导电接触由位于顶部电极下方的底部电极（图4d的304）构成的铁电电容器的顶部电极（图4d的308和310）和 铁电材料（图4d的306）位于顶部电极和底部电极之间，该方法包括以下步骤：在顶部电极上形成层（图4的408或312）; 在所述层中形成开口（图4d的414），以通过使用无氢蚀刻剂将所述开口蚀刻到所述层中来暴露所述顶部电极的一部分; 以及将导电材料（图4d的432）沉积在开口中以与顶部电极形成电连接。