公开(公告)号：US20150091600A1

公开(公告)日：2015-04-02

申请号：US14565724

申请日：2014-12-10

Applicant: HSIO TECHNOLOGIES, LLC.

Inventor： JAMES RATHBURN

IPC: G01R1/04 ,  G01R3/00

CPC classification number: G01R1/0466 ,  Y10T29/49222

Abstract: A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.

Abstract translation: 用于IC器件的测试插座包括具有至少一个中心层和第一和第二表面层的多层插座外壳。 第一和第二表面层的厚度和介电常数小于中心层的厚度和介电常数。 多个接触构件位于中心层的中心开口中，其远端延伸到第一层和第二层中的开口中。 接触构件的远端具有比第一和第二表面层中的开口更大的至少一个尺寸，以将接触构件保持在插座壳体中。 接触构件包括具有小于中心开口的直径的中心部分，使得在接触构件和中心层之间保持气隙。

公开(公告)号：US20150013901A1

公开(公告)日：2015-01-15

申请号：US14327916

申请日：2014-07-10

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： JAMES RATHBURN

IPC: H05K3/46 ,  H05K3/12 ,  H01L21/768 ,  H05K3/18

CPC classification number: H01L21/76877 ,  B33Y80/00 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0393 ,  H05K1/16 ,  H05K3/0005 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/429 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/09272 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/1476 ,  H01L2924/00014

Abstract: A system and method for “pixelating” a three-dimensional circuit structure into a three-dimensional matrix of cubes that are located with respect to a coordinate system. The design step is typically performed on a conventional computer using computer aided design software that pixelates the proposed circuit structure into an array of uniformly sized cube. The fabrication process involves adding and subtracting bulk materials from the individual cubic positions within the pixelated representation of the circuit structure. Various existing and new techniques can be used to add or subtract bulk materials as the cubic positions within the matrix to construct the circuit structure.

Abstract translation: 将三维电路结构“像素化”为相对于坐标系定位的三维矩阵的三维矩阵的系统和方法。 设计步骤通常在使用计算机辅助设计软件的常规计算机上执行，将所提出的电路结构像素化为均匀尺寸的立方体的阵列。 制造过程包括在电路结构的像素化表示内从各个立方体位置添加和减去大量材料。 可以使用各种现有技术和新技术将体积材料作为立方体位置加入或减去以构成电路结构。

公开(公告)号：US20150162678A1

公开(公告)日：2015-06-11

申请号：US14621663

申请日：2015-02-13

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： JAMES RATHBURN

IPC: H01R12/70 ,  H01R12/57

CPC classification number: H01R12/7082 ,  H01R12/57 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive.

Abstract translation: 一种互连组件，包括具有从第一表面延伸到第二表面的多个通孔的基底。 多个离散接触构件位于多个通孔中。 接触构件包括从第二表面可接近的近端，在第一表面上方延伸的远端，以及与位于第一表面和凹部之间的基底的接合区域接合的中间部分。 保持构件与至少一部分近端联接以将接触构件保持在通孔中。 保持构件可以由具有不同导电性的各种材料制成，从高导电性到非导电性。

公开(公告)号：US20160014908A1

公开(公告)日：2016-01-14

申请号：US14864215

申请日：2015-09-24

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： JAMES RATHBURN

IPC: H05K3/46 ,  B23K1/19 ,  B23K1/00 ,  H05K3/42 ,  B23K26/40 ,  C25D7/12 ,  C25D3/38 ,  B23K26/382 ,  B23K26/402

CPC classification number: H05K3/4623 ,  B23K2103/12 ,  B23K2103/30 ,  C23C18/1653 ,  C23C18/1689 ,  C23C18/38 ,  C25D5/022 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0393 ,  H05K3/421 ,  H05K3/429 ,  H05K3/4635 ,  H05K3/4679 ,  H05K2201/0141 ,  H05K2201/09563 ,  Y10T29/49002 ,  H01L2924/00014

Abstract: A method of making a multilayered, fusion bonded circuit structure. A first circuitry layer is attached to a first major surface of a first LCP substrate. A plurality of first recesses are formed that extend from a second major surface of the first substrate to the first circuitry layer. The first recesses are then plated to form a plurality of first conductive pillars of solid metal that substantially fill the first recesses. A plurality of second recesses are formed in a second LCP substrate corresponding to a plurality of the first conductive pillars. The second recess are plated to form a plurality of second conductive structures that extend between first and second major surfaces of the second substrate. The second major surface of the first substrate is positioned adjacent to the second major surface of the second substrate. The first conductive pillars are aligned with the second conductive structures. The stack is then fusion bonded to mechanically couple the first conductive pillars to the second conductive structures.

Abstract translation: 一种制造多层熔接电路结构的方法。 第一电路层附接到第一LCP衬底的第一主表面。 形成从第一基板的第二主表面延伸到第一电路层的多个第一凹槽。 然后电镀第一凹槽以形成基本上填充第一凹槽的多个固体金属的第一导电柱。 在对应于多个第一导电柱的第二LCP衬底中形成多个第二凹部。 电镀第二凹槽以形成在第二基底的第一和第二主表面之间延伸的多个第二导电结构。 第一基板的第二主表面邻近第二基板的第二主表面定位。 第一导电柱与第二导电结构对准。 然后将堆叠熔合以将第一导电柱机械地耦合到第二导电结构。

公开(公告)号：US20140080258A1

公开(公告)日：2014-03-20

申请号：US14086029

申请日：2013-11-21

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： JAMES RATHBURN

IPC: H01L23/00

CPC classification number: H01L24/82 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/185 ,  H01L2924/00

Abstract: A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.

Abstract translation: 一种制造具有电端子的半导体器件的封装的方法。 至少一个半导体器件位于衬底上。 在半导体器件的至少一部分上印刷第一电介质层以包括与多个电端子对准的第一凹部。 在形成接触构件的第一凹部中沉积导电材料。 第二电介质层印刷在第一电介质层的至少一部分上，以包括与多个第一凹槽对准的第二凹槽。 导电材料沉积在第二凹槽的至少一部分中以包括电路几何形状和多个暴露端子。 兼容材料沉积在与多个暴露端子相邻的第一和第二电介质层中的一个或多个中的凹槽中。