Method of manufacturing printed circuit board including outmost fine circuit pattern
    1.
    发明申请
    Method of manufacturing printed circuit board including outmost fine circuit pattern 审中-公开
    制造印刷电路板的方法包括最外面的精细电路图案

    公开(公告)号:US20120011716A1

    公开(公告)日:2012-01-19

    申请号:US13137695

    申请日:2011-09-02

    IPC分类号: H05K3/42

    摘要: A method of manufacturing a printed circuit board including: preparing a first double-sided substrate including a first insulating layer, a first lower copper layer, a second circuit layer including a first lower land, and a first via; preparing a second double-sided substrate including a second insulating layer, a third lower copper layer, a fourth circuit layer including a second lower land, and a second via; disposing a third insulating layer between the second circuit layer and the fourth circuit layer such that the first lower land and the second lower land are electrically connected to each other though a conductive bump; and forming a first circuit layer including a first circuit pattern connected to the first via on the first lower copper layer and forming a third circuit layer including a third circuit pattern connected to the second via on the third lower copper layer.

    摘要翻译: 一种制造印刷电路板的方法,包括:制备包括第一绝缘层,第一下铜层,包括第一下焊盘的第二电路层和第一通孔的第一双面基板; 制备包括第二绝缘层,第三下铜层,包括第二下焊盘的第四电路层和第二通孔的第二双面基板; 在所述第二电路层和所述第四电路层之间设置第三绝缘层,使得所述第一下焊盘和所述第二下焊盘通过导电凸块彼此电连接; 以及形成第一电路层,所述第一电路层包括在所述第一下铜层上连接到所述第一通孔的第一电路图案,并形成第三电路层,所述第三电路层包括在所述第三下铜层上连接到所述第二通孔的第三电路图案。

    Printed circuit board and method of manufacturing the same
    3.
    发明申请
    Printed circuit board and method of manufacturing the same 审中-公开
    印刷电路板及其制造方法

    公开(公告)号:US20090260868A1

    公开(公告)日:2009-10-22

    申请号:US12215413

    申请日:2008-06-27

    IPC分类号: H05K1/00 H05K3/42

    摘要: The printed circuit board includes the via formed with the electroplating layer unlike a conventional via formed with an electroless plating layer and an electroplating layer and having a cylindrical shape, and thus exhibits good interlayer electrical connection and high reliability of physical contact upon thermal stress caused by the variance in physical properties of material depending on changes in temperature. The via has no upper land, and thus a fine circuit pattern of the circuit layer can be formed on the via.

    摘要翻译: 印刷电路板包括形成有电镀层的通孔,与通过形成有化学镀层和电镀层并且具有圆柱形状的常规通孔不同,由此表现出良好的层间电连接和由于热应力引起的物理接触的高可靠性 材料的物理性质随温度变化的变化。 通孔没有上部焊盘,因此可以在通孔上形成电路层的精细电路图案。

    Printed circuit board having landless via hole and method of manufacturing the same
    4.
    发明申请
    Printed circuit board having landless via hole and method of manufacturing the same 审中-公开
    具有无通孔的印刷电路板及其制造方法

    公开(公告)号:US20090255722A1

    公开(公告)日:2009-10-15

    申请号:US12213975

    申请日:2008-06-26

    IPC分类号: H01R12/04 H05K3/00

    摘要: This invention relates to a printed circuit board having a landless via hole, including a circuit pattern formed on a via made of a first metal and having a line width smaller than the diameter of the via hole, in which the circuit pattern includes a seed layer made of a second metal and a plating layer made of a third metal, which is different from the second metal, and to a method of manufacturing the same. In the printed circuit board, the via has no upper land, thus making it possible to finely form the circuit pattern which is connected to the via, thereby realizing a high-density circuit pattern.

    摘要翻译: 本发明涉及一种具有无轨道通孔的印刷电路板,该无线通孔包括形成在由第一金属制成的通孔上并具有小于通孔直径的线宽的电路图案,其中电路图案包括种子层 由与第二金属不同的第三金属制成的第二金属和镀层制成,以及其制造方法。 在印刷电路板中,通孔没有上部焊盘,从而可以精细地形成连接到通孔的电路图案,从而实现高密度电路图案。

    Method of manufacturing printed circuit board having landless via hole
    5.
    发明授权
    Method of manufacturing printed circuit board having landless via hole 失效
    具有无通孔的印刷电路板的制造方法

    公开(公告)号:US08418361B2

    公开(公告)日:2013-04-16

    申请号:US13299685

    申请日:2011-11-18

    IPC分类号: H05K3/02

    摘要: Method of manufacturing printed circuit board, including: providing a substrate including a first circuit layer having a lower land of a via; forming an insulating layer on the first circuit layer; forming a via hole in the insulating layer; filling the via hole with a first metal, thus forming a via; forming a seed layer with a second metal on the insulating layer and an exposed surface of the via; applying a resist film on the seed layer, and forming a resist pattern having an opening for a second circuit layer with a width formed on the via being smaller than a width of the via; plating a circuit region defined by the opening with a third metal, thus forming a plating layer formed of the third metal; and removing the resist film, and selectively removing an exposed portion of the seed layer, thus forming a second circuit layer.

    摘要翻译: 制造印刷电路板的方法,包括:提供包括具有通孔下部的第一电路层的基板; 在所述第一电路层上形成绝缘层; 在绝缘层中形成通孔; 用第一金属填充通孔,从而形成通孔; 在绝缘层上形成具有第二金属的种子层和通孔的暴露表面; 在种子层上施加抗蚀剂膜,并且形成具有形成在通孔上的宽度的第二电路层的开口的抗蚀剂图案小于通孔的宽度; 用第三金属电镀由开口限定的电路区域,从而形成由第三金属形成的镀层; 并去除抗蚀剂膜,并且选择性地去除种子层的暴露部分,从而形成第二电路层。

    Carrier substrate, fabrication method thereof, printed circuit board using the same, and fabrication method thereof
    7.
    发明授权
    Carrier substrate, fabrication method thereof, printed circuit board using the same, and fabrication method thereof 失效
    载体基板,其制造方法,使用其的印刷电路板及其制造方法

    公开(公告)号:US08344261B2

    公开(公告)日:2013-01-01

    申请号:US12805586

    申请日:2010-08-06

    IPC分类号: H05K1/09 H05K1/11

    摘要: Disclosed are a carrier substrate including an insulating base material with a copper foil layer formed on at least one surface thereof, a metal layer formed on the copper layer and having a length shorter than that of the copper foil layer, and an insulating layer formed on the metal layer, a fabrication method thereof, a printed circuit board (PCB) using the same, and a fabrication method thereof. Because there is no land at the via and core in the substrate, because a circuit pattern connected with the via can be formed to be finer, so the circuit pattern can be highly integrated and the substrate can become thinner. Thus, a printed circuit board (PCB) having a smaller size and reduced number of layers can be fabricated.

    摘要翻译: 公开了一种载体基板,其包括在其至少一个表面上形成有铜箔层的绝缘基材,在铜层上形成的长度短于铜箔层的金属层,以及形成在 金属层,其制造方法,使用其的印刷电路板(PCB)及其制造方法。 由于在基板中的通孔和芯部没有焊盘,因为可以形成与通孔连接的电路图案更细,所以电路图案可以高度集成,并且基板可以变薄。 因此,可以制造具有更小尺寸和更少层数的印刷电路板(PCB)。

    Nano-imprint lithography methods
    9.
    发明授权
    Nano-imprint lithography methods 有权
    纳米压印光刻方法

    公开(公告)号:US08557130B2

    公开(公告)日:2013-10-15

    申请号:US12654023

    申请日:2009-12-08

    IPC分类号: C03C15/00 C03C25/68 C23F1/00

    摘要: In forming a pattern on a substrate with reduced pattern error using a mold having an area smaller than an area of the substrate, a first resin pattern is formed on at least a first of a plurality of regions of an etching object layer by imprinting resin applied to the etching object layer using a first mold The etching object layer is then etched using the first resin pattern as an etching mask. A second resin pattern is formed on at least a second of the plurality of regions by imprinting resin applied to the etching object layer using a second mold. The etching object layer is again etched using the second resin pattern as an etching mask.

    摘要翻译: 在使用面积小于基板的面积的模具的基板上形成图案减少图案的情况下,通过印刷树脂施加在蚀刻对象层的多个区域的至少第一区域上形成第一树脂图案 使用第一模具到蚀刻对象层。然后使用第一树脂图案作为蚀刻掩模蚀刻蚀刻对象层。 通过使用第二模具将施加到蚀刻对象层的树脂压印,在多个区域中的至少一个区域上形成第二树脂图案。 使用第二树脂图案作为蚀刻掩模再次蚀刻蚀刻对象层。