公开(公告)号：US08476763B2

公开(公告)日：2013-07-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US20120193792A1

公开(公告)日：2012-08-02

申请号：US13237514

申请日：2011-09-20

申请人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

发明人： Hei-Seung Kim ,  In-Sun Park ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee ,  Jong-Won Hong

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive pattern structures form an insulating interlayer on a substrate that is partially etched to form a first trench extending to both end portions of a cell block. The insulating interlayer is also partially etched to form a second trench adjacent to the first trench, and a third trench extending to the both end portions of the cell block. The second trench has a disconnected shape at a middle portion of the cell block. A seed copper layer is formed on the insulating interlayer. Inner portions of the first, second and third trenches are electroplated with a copper layer. The copper layer is polished to expose the insulating interlayer to form first and second conductive patterns in the first and second trenches, respectively, and a first dummy conductive pattern in the third trench. Related conductive pattern structures are also described.

摘要翻译： 形成导电图案结构的方法在被部分蚀刻以形成延伸到电池块的两端部的第一沟槽的衬底上形成绝缘中间层。 绝缘中间层也被部分蚀刻以形成与第一沟槽相邻的第二沟槽，以及延伸到电池块的两端部分的第三沟槽。 第二沟槽在电池块的中间部分具有断开的形状。 在绝缘中间层上形成种子铜层。 第一，第二和第三沟槽的内部部分用铜层电镀。 抛光铜层以暴露绝缘中间层，以分别在第一和第二沟槽中形成第一和第二导电图案，并在第三沟槽中形成第一虚设导电图案。 还描述了相关的导电图案结构。

公开(公告)号：US08592979B2

公开(公告)日：2013-11-26

申请号：US13440123

申请日：2012-04-05

申请人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

发明人： Hei-Seung Kim ,  Gil-Heyun Choi ,  Ji-Soon Park ,  Jong-Myeong Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/11524 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/528 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.

摘要翻译： 导电图案结构包括在基板上的第一绝缘中间层，第一绝缘中间层上的金属布线，金属布线上的第二绝缘中间层以及延伸穿过第二绝缘夹层的第一和第二金属触点。 第一金属触点与单元区域中的金属布线接触，并且第二金属触点与外围区域中的金属布线接触。 第三绝缘中间层设置在第二绝缘中间层上。 导电部分延伸通过电池区域中的第三绝缘中间层并与第一金属触点接触。 另一个导电段延伸穿过周边区域中的第三绝缘中间层并接触第二金属接触。 该结构有助于使用电镀工艺在电池区域中形成均匀厚的布线。

公开(公告)号：US09355851B2

公开(公告)日：2016-05-31

申请号：US13588393

申请日：2012-08-17

申请人： Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-hee Nam ,  In-sun Park ,  Jong-Myeong Lee

发明人： Jong-Won Hong ,  Hei-Seung Kim ,  Kyoung-hee Nam ,  In-sun Park ,  Jong-Myeong Lee

IPC分类号： H01L21/762 ,  H01L21/763 ,  H01L21/288 ,  H01L23/532 ,  H01L27/115 ,  H01L21/768 ,  H01L27/108

CPC分类号： H01L21/76879 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76861 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53238 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a metal pattern filling a trench formed through at least a portion of an insulating interlayer on a substrate and including copper, and a wetting improvement layer pattern in the metal pattern including at least one of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, cobalt and manganese.

摘要翻译： 半导体器件包括填充通过衬底上的绝缘中间层的至少一部分形成并包括铜的沟槽的金属图案，以及金属图案中的包含钽，氮化钽，钛，钛中的至少一种的润湿改善层图案 氮化物，钌，钴和锰。

公开(公告)号：US08889543B2

公开(公告)日：2014-11-18

申请号：US13795807

申请日：2013-03-12

申请人： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

发明人： Jong-Min Baek ,  In-Sun Park ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hei-Seung Kim ,  Jung-Soo Yoon

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76804 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76885

摘要： A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.

摘要翻译： 制造半导体器件的方法包括在衬底上形成开关器件。 在具有开关装置的基板中形成下部结构。 下导电层形成在下结构上。 牺牲掩模图案形成在下导电层上。 通过使用牺牲掩模图案作为蚀刻掩模蚀刻下导电层来形成下导电图案。 在具有较低导电图案的基板上形成层间绝缘层。 通过平坦化层间绝缘层直到牺牲掩模图案曝光来形成层间绝缘图案。 通过去除暴露的牺牲掩模图案来形成露出下导电图案的开口。 在开口中形成与下导电图案自对准的上导电图案。