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1.发明授权Field effect transistor having impurity regions of different depths and manufacturing method thereof 失效具有不同深度的杂质区域的场效应晶体管及其制造方法
公开(公告)号：US5672533A
公开(公告)日：1997-09-30
申请号：US555414
申请日：1995-11-09
IPC分类号： H01L21/8242 , H01L29/68 , H01L29/76 , H01L29/78 , H01L29/92 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L27/1085 , H01L27/10891 , H01L27/10894 , H01L29/66659
摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.
摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。
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2.发明授权Field effect transistor having impurity regions of different depths and manufacturing method thereof 失效具有不同深度的杂质区域的场效应晶体管及其制造方法
公开(公告)号：US5489791A
公开(公告)日：1996-02-06
申请号：US100950
申请日：1993-08-03
IPC分类号： H01L21/8242 , H01L29/68 , H01L29/76 , H01L29/78 , H01L29/92 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L27/1085 , H01L27/10891 , H01L27/10894 , H01L29/66659
摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.
摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。
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3.发明授权Field effect transistor having impurity regions of different depths and manufacturing method thereof 失效具有不同深度的杂质区域的场效应晶体管及其制造方法
公开(公告)号：US5276344A
公开(公告)日：1994-01-04
申请号：US13500
申请日：1993-02-02
IPC分类号： H01L21/8242 , H01L29/68 , H01L29/76 , H01L29/78 , H01L29/92 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L27/1085 , H01L27/10891 , H01L27/10894 , H01L29/66659
摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.
摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。
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4.发明授权Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region 失效在存储器单元区域和外围电路区域的边界区域具有外围壁的半导体存储器件
公开(公告)号：US5218219A
公开(公告)日：1993-06-08
申请号：US678872
申请日：1991-04-04
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10817
摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.
摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。
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5.发明授权Method of manufacturing a semiconductor memory device with multiple device forming regions 失效制造具有多个器件形成区域的半导体存储器件的方法
公开(公告)号：US5364811A
公开(公告)日：1994-11-15
申请号：US17901
申请日：1993-02-16
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.
摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。
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6.发明授权Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension 失效具有栅极电极间距的半导体器件与栅极侧壁绝缘尺寸相关
公开(公告)号：US5233212A
公开(公告)日：1993-08-03
申请号：US692395
申请日：1991-04-25
申请人： Makoto Ohi , Hideaki Arima , Natsuo Ajika , Atsushi Hachisuka , Yasushi Matsui
发明人： Makoto Ohi , Hideaki Arima , Natsuo Ajika , Atsushi Hachisuka , Yasushi Matsui
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L21/76801 , H01L21/76834 , H01L27/10808 , Y10S257/90
摘要： A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.
摘要翻译： 半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了栅电极的顶部和侧壁。 在元件隔离区域（2）的表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁的绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于树脂膜的过度蚀刻而导致的断开。
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7.发明授权Method of making a semiconductor integrated device having gate sidewall structure 失效制造具有栅极侧壁结构的半导体集成器件的方法
公开(公告)号：US5338699A
公开(公告)日：1994-08-16
申请号：US10691
申请日：1993-01-29
申请人： Makoto Ohi , Hideaki Arima , Natsuo Ajika , Atsushi Hachisuka , Yasushi Matsui
发明人： Makoto Ohi , Hideaki Arima , Natsuo Ajika , Atsushi Hachisuka , Yasushi Matsui
IPC分类号： H01L27/04 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L21/76801 , H01L21/76834 , H01L27/10808 , Y10S257/90
摘要： A method of making a semiconductor device including a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) are smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resist film in patterning the conductive interconnection layer.
摘要翻译： 一种制造半导体器件的方法，该半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了顶部和侧壁 栅电极。 元件隔离区域（2）表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于抗蚀剂膜的过度蚀刻而导致的断开。
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8.发明授权Dynamic random access memory having stacked type capacitor and manufacturing method therefor 失效具有层叠型电容器的动态随机存取存储器及其制造方法
公开(公告)号：US5381365A
公开(公告)日：1995-01-10
申请号：US91675
申请日：1993-06-30
申请人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
发明人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
IPC分类号： H01L27/108 , H01L29/68 , H01L27/10
CPC分类号： H01L27/10817
摘要： The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.
摘要翻译： 根据本发明的DRAM包括所谓的圆柱形堆叠型电容器。 每个圆柱形堆叠型电容器包括在绝缘层和基板的表面上平坦延伸的基部，以及从基部垂直和向上延伸的圆柱形部分。 然后，圆筒部从基部的最外周位置向上方突出。 结果，可以增加电容器的电极和电容器的电容的区域。 此外，通过位于电容器的电极层下方的位线，可以隔离位线上方的相邻电容器。 因此，可以防止位线接触限定电容器之间的隔离距离。 此外，通过蚀刻图案化的隔离层用作电容器之间的隔离区域，并且电容器的下电极沿着隔离层的表面形成，以在相邻的电容器之间形成隔离区域。 此外，圆柱形堆叠型电容器的下电极通过使用形成在绝缘层中的台阶整体地形成。 结果，简化了制造步骤。
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公开(公告)号：US5597755A
公开(公告)日：1997-01-28
申请号：US457193
申请日：1995-06-01
申请人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
发明人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817 , H01L27/10852
摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.
摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。
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10.发明授权Method of manufacturing stacked capacitors in a DRAM with reduced isolation region between adjacent capacitors 失效在相邻电容器之间具有减小的隔离区域的DRAM中制造叠层电容器的方法
公开(公告)号：US5798289A
公开(公告)日：1998-08-25
申请号：US716851
申请日：1996-09-10
申请人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
发明人： Natsuo Ajika , Hideaki Arima , Atsushi Hachisuka
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/10852
摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.
摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。
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