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    Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip
    2.
    发明授权
    Single-chip semiconductor integrated circuit device and microcomputer integrated on a semiconductor chip 失效
    集成在半导体芯片上的单片半导体集成电路器件和微计算机

    公开(公告)号：US5784637A

    公开(公告)日：1998-07-21

    申请号：US414157

    申请日：1995-03-31

    申请人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    发明人： Terumi Sawase ,  Kouki Noguchi ,  Hideo Nakamura ,  Yasushi Akao ,  Shiro Baba ,  Yoshimune Hagiwara

    IPC分类号： G06F9/24 ,  G06F15/78

    CPC分类号： G06F9/24 ,  G06F15/7814

    摘要： A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.

    摘要翻译： 形成在集成在半导体芯片上的单个芯片或微计算机上的半导体集成电路装置包括中央处理单元（CPU），接口电路（或输入/输出端口），耦合到CPU和接口电路的总线 或输入/输出端口）和可变逻辑电路（或子处理器）。 可变逻辑电路（或子处理器）包括存储指令的非易失性存储器元件，根据存储的指令产生控制信号的控制电路以及由所生成的控制信号控制的算术逻辑单元。 可以从外部将信息写入非易失性存储器元件，以任何期望的逻辑功能构建可变逻辑电路或子处理器。 存储元件的布线操作可以在短时间内执行，因此用户可以快速获得具有特定规定规格的硬件的单芯片微处理器或单芯片半导体集成电路器件。

    Single chip microprocessor for satisfying requirement specification of users
    3.
    发明授权
    Single chip microprocessor for satisfying requirement specification of users 失效
    单芯片微处理器，用于满足用户的要求规格

    公开(公告)号：US5426744A

    公开(公告)日：1995-06-20

    申请号：US203761

    申请日：1994-03-01

    申请人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

    发明人： Terumi Sawase ,  Yoshimune Hagiwara ,  Hideo Nakamura ,  Hiroyuki Hatori ,  Shirou Baba ,  Yasushi Akao

    IPC分类号： G06F9/24 ,  G06F9/38 ,  G06F11/267 ,  G06F15/78 ,  G06F9/26

    CPC分类号： G06F9/3879 ,  G06F11/2236 ,  G06F15/7814 ,  G06F15/7867 ,  G06F9/24 ,  G06F9/3897

    摘要： A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.

    摘要翻译： 本申请中公开的典型的单片机包括控制电路，处理电路和多个地址寄存器状态寄存器对。 形成在控制电路内的逻辑单元包括电可写非易失性半导体存储器件。 信息可以被外部写入包括在逻辑单元中的非易失性半导体存储器中，并且可以任意地选择上述多个地址寄存器状态寄存器对。 结果，可以根据外部提供的信息任意地建立逻辑单元的逻辑功能。 可以通过任意形成的逻辑功能来满足各种用户的需求规格。

    Method of diagnosing integrated logic circuit
    4.
    发明授权
    Method of diagnosing integrated logic circuit 失效
    诊断集成逻辑电路的方法

    公开(公告)号：US4996659A

    公开(公告)日：1991-02-26

    申请号：US84153

    申请日：1987-08-12

    申请人： Noboru Yamaguchi ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Tsukasa Sato ,  Haruo Koizumi

    发明人： Noboru Yamaguchi ,  Hideo Nakamura ,  Yoshimune Hagiwara ,  Tsukasa Sato ,  Haruo Koizumi

    IPC分类号： G01R31/305 ,  G01R31/3193

    CPC分类号： G01R31/3193 ,  G01R31/305

    摘要： A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.

    摘要翻译： 一种诊断具有功能块的集成逻辑电路的方法，其中测试信号被提供给逻辑电路; 通过使用诸如电子束探测装置或激光束探测装置的非接触探测装置来检测来自至少一个功能块的输入信号和输出信号; 利用检测到的输入信号对功能块的正常逻辑运算进行仿真，以提供模拟输出信号; 检测和模拟的输出信号相互比较; 并且根据比较的结果将功能块确定为正常或异常。 当功能块包括多个逻辑元件时，通过非接触探测装置检测功能元件的输出，将检测到的输出与对应的模拟输出进行比较并重复检测，可以将异常的原因追溯到故障功能元件 并比较功能块中的其他功能元素，直到比较结果重合。 将作为比较结果提供一致的信号的功能元件确定为故障功能元件。

    Digital signal processor suitable for extacting minimum and maximum values at high speed
    5.
    发明授权
    Digital signal processor suitable for extacting minimum and maximum values at high speed 失效
    数字信号处理器适用于高速度的最小值和最大值

    公开(公告)号：US4967349A

    公开(公告)日：1990-10-30

    申请号：US140792

    申请日：1988-01-05

    申请人： Kazuyuki Kodama ,  Hirotada Ueda ,  Kenji Keneko ,  Yoshimune Hagiwara ,  Hitoshi Matsushima

    发明人： Kazuyuki Kodama ,  Hirotada Ueda ,  Kenji Keneko ,  Yoshimune Hagiwara ,  Hitoshi Matsushima

    IPC分类号： G06F7/02 ,  G06F9/22 ,  G06F17/10 ,  G06F17/18

    CPC分类号： G06F17/18

    摘要： A digital signal processor for determining the maximum and minimum values of a plurality of data items wherein operations of an arithmetic logic unit and data memories are controlled by micro-instructions, including a device for decoding specified bits of an operand of the micro-instruction, a device for detecting a value of a condition code which has been designated by an output of the decoding device, and a control device for executing a logical operation between the output of the detection device, which becomes "1" if the value of the condition code is true, and a decoded value of an operation code of the micro-instruction and to generate a control signal for the arithmetic logic unit on the basis of a result of the logical operation.

    摘要翻译： 一种用于确定多个数据项的最大值和最小值的数字信号处理器，其中，所述算术逻辑单元和数据存储器的操作由微指令控制，所述微指令包括用于解码所述微指令的操作数的指定位的设备， 用于检测由解码装置的输出指定的条件码的值的装置，以及用于在检测装置的输出之间执行逻辑运算的控制装置，如果条件的值为“1” 代码为真，以及微指令的操作码的解码值，并且基于逻辑运算的结果生成运算逻辑单元的控制信号。

    Processor capable of executing one or more programs by a plurality of operation units
    6.
    发明授权
    Processor capable of executing one or more programs by a plurality of operation units 失效
    处理器能够由多个操作单元执行一个或多个程序

    公开(公告)号：US4821187A

    公开(公告)日：1989-04-11

    申请号：US794449

    申请日：1985-11-04

    申请人： Hirotada Ueda ,  Hitoshi Matsushima ,  Yoshimune Hagiwara ,  Kenji Kaneko

    发明人： Hirotada Ueda ,  Hitoshi Matsushima ,  Yoshimune Hagiwara ,  Kenji Kaneko

    IPC分类号： G06F15/16 ,  G06F9/28 ,  G06F9/38 ,  G06F17/16 ,  G06T1/00 ,  G06T1/20

    CPC分类号： G06F9/28 ,  G06F9/3885

    摘要： A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.

    摘要翻译： 处理器包括第一和第二操作单元，第一程序存储器，其包含用于控制第一操作单元的第一微指令和用于至少控制第二操作单元的第二微指令;第二程序存储器，其包含用于控制第二操作单元的微指令， 连接到第一程序存储器用于控制第一操作单元和第二操作单元的控制装置，以及连接到第二程序存储器用于控制第二操作单元的第二控制装置。 在正常模式中，所有操作单元都受到第一控制装置的控制，并且在多路程序模式中，第一操作单元处于第一控制装置的控制之下，第二操作单元处于第二控制装置的控制之下。 根据存储在第一或第二程序存储器中的微指令来选择这两个模式操作。

    Address translation unit
    7.
    发明授权
    Address translation unit 失效
    地址翻译单位

    公开(公告)号：US4812969A

    公开(公告)日：1989-03-14

    申请号：US865840

    申请日：1986-05-22

    申请人： Katsuaki Takagi ,  Hirokazu Aoki ,  Norio Nakagawa ,  Yoshimune Hagiwara

    发明人： Katsuaki Takagi ,  Hirokazu Aoki ,  Norio Nakagawa ,  Yoshimune Hagiwara

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F9/32 ,  G06F9/36

    CPC分类号： G06F12/1036

    摘要： An address translation unit for use in a computer system having a multi-virtual space comprises a full associative translation lookaside buffer (TLB) which includes, for each entry, an associative memory array which stores and compares addresses. The associative memory array is provided with a circuit which, when a specific value is set in a common area field, invalidates comparison in a space number field.

    摘要翻译： 在具有多虚拟空间的计算机系统中使用的地址转换单元包括全关联翻译后备缓冲器（TLB），其对于每个条目包括存储和比较地址的关联存储器阵列。 关联存储器阵列设置有当在公共区域字段中设置特定值时使空格号字段中的比较无效的电路。