公开(公告)号：US4455495A

公开(公告)日：1984-06-19

申请号：US192869

申请日：1980-10-01

申请人： Toshiaki Masuhara ,  Osamu Minato ,  Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Hideo Sunami ,  Yoshio Sakai ,  Yoshiaki Kamigaki ,  Eiji Takeda ,  Yoshimune Hagiwara

发明人： Toshiaki Masuhara ,  Osamu Minato ,  Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Hideo Sunami ,  Yoshio Sakai ,  Yoshiaki Kamigaki ,  Eiji Takeda ,  Yoshimune Hagiwara

IPC分类号： G11C8/10 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  H01L21/263 ,  H01L21/268 ,  H01L21/768 ,  H01L23/525 ,  H01L27/10 ,  H01L27/04 ,  H01L29/04

CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C17/18 ,  G11C8/10 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/76894 ,  H01L23/5254 ,  H01L27/10 ,  H01L2924/0002

摘要： A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.

摘要翻译： 公开了一种包括电路编程元件的可编程半导体集成电路。 电路编程元件可以通过激光或电子束的照射或通过离子注入在短路模式中被激活，使得其从其原始的非导通状态转换为导电或导电状态，由此提供电路之间的电连接 /或集成电路的电路元件，用于所需的电路编程，例如电路创建，电路转换或电路替换。

公开(公告)号：US4656492A

公开(公告)日：1987-04-07

申请号：US786715

申请日：1985-10-15

申请人： Hideo Sunami ,  Hiroo Masuda ,  Yoshiaki Kamigaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda

发明人： Hideo Sunami ,  Hiroo Masuda ,  Yoshiaki Kamigaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7838 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/78 ,  H01L29/7836

摘要： An insulated gate field effect transistor is formed in one surface of a semiconductor substrate. The surface portion of a channel has an impurity distribution of the conduction type opposite to that of the substrate, which the deeper portion of the channel has an impurity distribution of the same conduction type as that of the substrate. Moreover, at least one of a source and a drain is formed of such an impurity layer of the conduction type opposite to that of the substrate as has its impurity distribution gently sloped by double diffusion processes.

摘要翻译： 绝缘栅场效应晶体管形成在半导体衬底的一个表面中。 通道的表面部分具有与衬底相反的导电类型的杂质分布，其中沟道的较深部分具有与衬底相同导电类型的杂质分布。 此外，源极和漏极中的至少一个由具有与衬底相反的导电类型的杂质层形成，其杂质分布通过双扩散过程缓缓倾斜。

公开(公告)号：US5237528A

公开(公告)日：1993-08-17

申请号：US822325

申请日：1992-01-17

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。

公开(公告)号：US5214496A

公开(公告)日：1993-05-25

申请号：US452683

申请日：1989-12-19

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L27/10829 ,  G11C11/404 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

公开(公告)号：US4901128A

公开(公告)日：1990-02-13

申请号：US934556

申请日：1986-11-24

申请人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

发明人： Hideo Sunami ,  Tokuo Kure ,  Masanobu Miyao ,  Yoshifumi Kawamoto ,  Katsuhiro Shimohigashi ,  Yoshio Sakai ,  Osamu Minato ,  Toshiaki Masuhara ,  Mitsumasa Koyanagi ,  Shinji Shimizu

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/94

CPC分类号： G11C11/404 ,  H01L27/10829 ,  H01L27/10841 ,  H01L29/945

摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.

摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。

公开(公告)号：US5132771A

公开(公告)日：1992-07-21

申请号：US503928

申请日：1990-04-04

申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

公开(公告)号：US4805147A

公开(公告)日：1989-02-14

申请号：US871994

申请日：1986-06-09

申请人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Tetsuya Hayashida ,  Osamu Minato ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

发明人： Toshiaki Yamanaka ,  Yoshio Sakai ,  Tetsuya Hayashida ,  Osamu Minato ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

IPC分类号： H01L27/04 ,  G11C11/412 ,  H01L21/265 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C11/4125 ,  H01L27/11 ,  H01L27/1112 ,  Y10S257/904 ,  Y10S257/906

摘要： A static random access memory cell in which capacitors are electrically connected to storage nodes, so that the memory cell will not suffer from soft error even when it is hit by alpha particles. The memory cell has MOS transistors, capacitors constituted by two polycrystalline silicon layers, and resistors constituted by a polycrystalline silicon layer, that are formed on a semiconductor substrate.

摘要翻译： 其中电容器电连接到存储节点的静态随机存取存储单元，使得即使存储单元被α粒子撞击也不会遭受软错误。 存储单元具有形成在半导体衬底上的MOS晶体管，由两个多晶硅层构成的电容器和由多晶硅层构成的电阻器。

公开(公告)号：US4849801A

公开(公告)日：1989-07-18

申请号：US113381

申请日：1987-10-27

申请人： Shigeru Honjyo ,  Osamu Minato ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

发明人： Shigeru Honjyo ,  Osamu Minato ,  Yoshio Sakai ,  Toshiaki Yamanaka ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara

IPC分类号： H01L29/94 ,  G11C11/41 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/1112 ,  Y10S257/903

摘要： A semiconductor memory device is provided in which an electrode applied with the power supply voltage or the ground voltage is provided on an insulating layer over the drain and/or the gate of the MOS transistors constituting the memory cell of a static memory device, thereby to increasing the capacitance of the storing node of the memory cell. This semiconductor memory device significantly reduces the occurrence of soft errors.

摘要翻译： 提供一种半导体存储器件，其中施加有电源电压或接地电压的电极设置在构成静态存储器件的存储单元的MOS晶体管的漏极和/或栅极上的绝缘层上，从而 增加存储单元的存储节点的电容。 该半导体存储器件显着地减少了软错误的发生。

公开(公告)号：US4701884A

公开(公告)日：1987-10-20

申请号：US896257

申请日：1986-08-14

申请人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

发明人： Masakazu Aoki ,  Masashi Horiguchi ,  Yoshinobu Nakagome ,  Shinichi Ikenaga ,  Katsuhiro Shimohigashi ,  Toshiaki Masuhara ,  Kiyoo Itoh ,  Hideo Nakamura ,  Osamu Minato

IPC分类号： G11C11/56 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C11/565 ,  H01L27/10805

摘要： A semiconductor memory device is proposed wherein at least an array comprising a plurality of memory cells each having at least one capacity, a select mechanism for specifying the position of each memory cell, data lines connected to said memory cells for transmitting the data and a data writing and a data reading mechanisms are provided. The feature of this device lies in that the voltage generator for serially generating three or more values of the voltage which are different from each other and the means for applying said voltage to said memory cells are provided on the same semiconductor board as the same said memory cells, and as the said reading mechanism the column register is provided which, as said reading mechanism, has the mechanism for deciding the data, transfer gate which is provided between said deciding means and said data line, and the bias charge transfer mechanism which is provided between said transfer gate and said deciding mechanism, and having at least two or more memory elements for temporarily storing said decided data.

摘要翻译： 提出了一种半导体存储器件，其中至少包括多个具有至少一个容量的存储单元的阵列，用于指定每个存储单元的位置的选择机构，连接到所述存储器单元的用于发送数据的数据线和数据 提供写入和数据读取机制。 该装置的特征在于，用于串联产生彼此不同的三个或更多个电压值的电压发生器和用于将所述电压施加到所述存储单元的装置设置在与所述存储器相同的半导体板上 并且作为所述读取机构，列寄存器被提供，其作为所述读取机构具有用于确定数据的机制，所述决定装置和所述数据线之间提供的传送门和作为所述读取机构的偏置电荷传送机构 提供在所述传送门和所述判定机构之间，并且具有用于临时存储所述决定的数据的至少两个或更多个存储器元件。

公开(公告)号：US4747082A

公开(公告)日：1988-05-24

申请号：US76174

申请日：1987-07-21

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

IPC分类号： G11C11/406 ,  G11C8/00

CPC分类号： G11C11/406

摘要： A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

摘要翻译： 半导体存储器设置有自动刷新装置，包括定时器，刷新计数器和刷新缓冲器，每个形成在安装有异步存储器的半导体芯片上，用于基于生成的基本时钟信号自动执行周期性刷新操作 响应于对刷新计数器的输出的逻辑改变的检测。 自动刷新计数器包括优先于周期性刷新操作执行基于与周期性刷新操作异步的常规地址信号的读操作和写操作之一的装置。